Wireless Ad Hoc and Sensor Networks

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Optimized Energy and Delay-Based Routing 415optimal routing calculations in energy and delay dependent environments.The use of hardware developed at the University of Missouri–Rolla (UMR)is shown as a development platform for this implementation.Available routing protocols such as data-centric, location-based, QoSaware, and hierarchical for WSNs have been evaluated in simulation.However, there are few, or no, experimental results reported as to howthey perform on hardware. In this section (Fonda et al. 2006), the focus ison hardware implementation of OEDSR protocol and its assessment.This section from Fonda et al. (2006) will present the performance evaluationof OEDSR through hardware implementation. An 8-bit 8051 variantmicrocontroller-based implementation platform utilizing 802.15.4 RF communicationunits is shown. The use of this platform provides high-speedprocessing, interconnectivity with sensors, and a capable RF communicationsunit to facilitate a development platform for WSN. The hardwaredescription includes considerations and limitations that the algorithm andhardware incur on one another. A description of the software implementationis next described.8.10.1 Hardware Implementation DescriptionIn this section, an overview of the hardware implementation of the OEDSRprotocol is given. Use of customized hardware for development of sensing,processing, and networking will be presented. A description of capabilities,limitations, and support for networking applications are given next. Also, inthis section, an overview of the software architectures is given with respectto the routing protocol and its memory requirements on the hardware.Hardware for implementation of the OEDSR was selected to be energyconservative, performance-oriented, and of small form-factor. Use of SiliconLaboratories ® 8051 variant hardware was selected for its ability toprovide fast 8-bit processing, low power consumption, and ease of interfacingto peripheral hardware components. Next, a treatment of the hardwarecapabilities and limitations will be given.Hardware implementation of any algorithm is constrained by the limitationsof the hardware. Use of specific hardware must be weighed againstthe precision, speed, and criticality of an algorithm’s implementation. Constraintsaddressed for the implementation of the OEDSR were the use oflow-power, small form-factor, and fast processing hardware. For this protocol,low power consumption was given the highest priority. In turn, thedemand for low power limits the types of processor architectures that canbe deployed. The selection of the Silicon Laboratories ® 8051 variants wasbased on these criteria. Limitations for the implementation that are incurredthrough the use of the 8051 variant family are a small memory space anda maximum processing speed. In the next section, a description of thespecifications for the hardware-implemented nodes will be given.
416 Wireless Ad Hoc and Sensor NetworksFIGURE 8.49(a) Instrumentation Sensor Node (ISN) and (b) Generation-4 Smart Sensor Node (G4-SSN).8.10.1.1 Architecture of the Hardware System and SoftwareNow, a discussion of hardware and software resources employed forimplementation of the OEDSR is given. A hardware performance comparisonof sensor node platforms used at UMR is shown. Software implementationin terms of architecture, control-flow, and hardware limitationsis shown.8.10.1.2 Sensor Node: Instrumentation Sensor NodeThe UMR Instrumentation Sensor Node (ISN), as seen in Figure 8.49a, isused for interfacing sensors to CHs. The ISN allows a sensor to be monitoredby a small and low-power device that can be controlled by CHswhich is also another node. In this application, the ISN is used as thesource of sensor traffic. The ISN is capable of being interfaced with severalsensor types and can be instructed by control packets to transmit data inraw or preprocessed form.8.10.1.3 Cluster Head and Relay NodesThe Generation-4 Smart Sensor Node (G4-SSN), seen in Figure 8.49b,originally developed at UMR and subsequently updated at St. Louis University,was chosen as the CH. The G4-SSN has various abilities for sensingand processing. The former include strain gauges, accelerometers, thermocouples,and general A/D sensing. The latter include analog filtering,CF memory interfacing, and 8-bit data processing at a maximum of 100MIPS. The G4-SSN provides memory and speed advantages over the ISNthat make it a suitable choice for implementation as a CH or an RN. Future
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18. Chaos in Automatic Control, edi
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CRC PressTaylor & Francis Group6000
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Table of Contents1 Background on Ne
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3 Congestion Control in ATM Network
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5.4.2 Distributed Power Controller
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7.3 Adaptive and Distributed Fair S
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9.2.2 Overview.....................
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the number of connections in each l
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y Maheswaran Thiagarajan, and tirel
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2 Wireless Ad Hoc and Sensor Networ
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10 Wireless Ad Hoc and Sensor Netwo
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2BackgroundIn this chapter, we prov
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Background 51u(k)x n (k + 1)x n (k)
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Background 53with x( 0)being the in
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Background 55with tr(.) the matrix
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Background 57nGiven a function ft (
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Background 592.3.2 Lyapunov Stabili
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Background 61as well as Jagannathan
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Background 63The subsequent example
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Background 65Evaluating this along
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Background 67Now, select the feedba
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Background 69is SISL if and only if
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Background 71L 1 (x)L(x, t)L 0 (x)0
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Background 73for some R > 0 such th
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Background 75Evaluating the first d
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Background 77Section 2.4Problem 2.4
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100 Wireless Ad Hoc and Sensor Netw
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7Distributed Fair Scheduling in Wir
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Distributed Fair Scheduling in Wire
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8Optimized Energy and Delay-Based R
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