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DESIGN FLOW
WITH DIMEtalk
Connect Algorithms
Import algorithms as
HDL code or Xilinx
compatible netlist
and connect into the
DIMEtalk network
Synthesis
Synthesize whole
design using
standard synthesis
tools
Figure 2 – DIMEtalk design flow
We are not suggesting that DIMEtalk
networks should completely replace other
types of data networks. However, within
FPGAs and going between FPGAs on the
same card, a low-resource, easy-to-implement
network such as DIMEtalk makes
sense – as demonstrated by the resource
usage shown in Figure 1.
DIMEtalk is intended to be used alongside
other data network and backplane
Figure 3 – Hardware
for example system
Network Definition
Define DIMEtalk
network for FPGA
computing system
using DIMEtalk
software tool
Assign to Devices
Assign network to
FPGAs and use
Device Editor to
drag and drop port
signals to the FPGA
UCF I/O signals
Implementation
Implement design
using standard
implementation tools
Develop Algorithms
Develop rest of
application using
standard design entry
flows (HDL, System
Generator, AccelFPGA,
Handel-C, etc.)
Generate Code
DIMEtalk
automatically
generates HDL code
and user constraints
files for complete
design
Runtime
Appl ication operating in
runtime, using DIMEtalk
API functions to
communicate across
DIMEtalk network
types – that’s why the edge components are
so important. The edges enable you to use
low-resource DIMEtalk networks where it
is right to do so and interface directly to
other protocols off-card.
Using DIMEtalk
DIMEtalk is designed to make life easier
for developers to deploy applications on an
FPGA computing platform. The intuitive
Xilinx
Virtex-II
2V6000
FPGA
VME
Interface
Xilinx
Virtex-II
2V6000
FPGA
Xilinx
Virtex-II
2V6000
FPGA
design flow shown in Figure 2 enables easy
network implementation and you can use
the design-entry tool of your choice for
algorithm blocks. The stages of the design
flow are:
• Network Definition – conceptually
design the network to provide communications
links and interface points to
algorithms as required across the FPGAs
• Develop Algorithms – use HDL or
other tools to develop algorithm blocks
using HDL or other design flows connected
to the interface nodes of the
DIMEtalk network
• Connect Algorithms – connect the
completed algorithm blocks to the
network; at this stage, the network and
application are functionally complete
• Assign to Devices – assign the whole
design to FPGAs using a drag-anddrop
feature
• Code Generation – automatic code
generation for design
• Synthesis – using standard synthesis
tools
• Implementation – using the Xilinx ISE
software tool flow
Xilinx
Virtex-II Pro
2VP50
FPGA
SRAM SRAM SRAM SRAM SRAM SRAM
Xilinx
Virtex-II
2V6000
FPGA
Figure 4 – Hardware block diagram for example system
106 Xcell Journal Winter 2004
SRAM
SRAM
Gigabit Ethernet