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DIGITAL SIGNAL PROCESSING Implementing DSP Algorithms in FPGAs A detailed overview of Xilinx System Generator for DSP, using a QAM system design example. by Sabine Lam DSP Technical Marketing Engineer Xilinx, Inc. sabine.lam@xilinx.com Today, the role of FPGAs in the DSP market is well understood – there simply is no better way to create ultra-fast DSP applications. Yet combining these two technologies can be a challenge – DSP designers primarily use The MathWorks MAT- LAB or C/C++ to specify systems, whereas FPGA designers use VHDL or Verilog. The only common approach between these two is that they often start with a block diagram. DSP architects and FPGA designers have two completely different backgrounds, yet they must work together to create an optimum product. Their focus and expertise do not overlap, and as a result, they often have difficulty communicating. The team must verify that the FPGA implementation does indeed match the original specification given by the DSP architect, and usually they must modify the DSP algorithm to obtain the best possible implementation in the FPGA. This requires a constant exchange of information about simulation results, design size, design performance, DSP algorithm changes, and implementation results throughout the design process. 56 Xcell Journal Winter 2004
The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. Deciding on a single tool and a language that meets the requirements of the whole design team can be difficult, especially when budgets are low and turnaround times are short. What could be better than an environment understood by the entire team, using a single source code? Sine Wave dbl fpt din In1 Transmitter: FEC and QAM Symbol Mapping dbl fpt dbl fpt q_in System Generator Xilinx ® System Generator is a system-level modeling tool that facilitates FPGA hardware design. It extends The MathWorks Simulink in many ways to provide a modeling environment well suited to hardware design. The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through lower-level abstractions, allowing the construction of highly efficient FPGA designs. It is delivered along with a predefined Xilinx blockset library, but also allows access to other languages with which most FPGA designers are familiar. Finally, it offers the ability to design at a system level, and allows simulation, implementation, and verification within the same environment, usually fpt dbl i_out fpt dbl q_out Phase Offset without writing a single line of HDL code or even looking at the Xilinx ISE tools. To highlight the System Generator design flow, we will use a Quadrature Amplitude Modulator (QAM) system design example (Figure 1), implemented according to the specifications provided by A QAM System with Packet Framing and FEC for Telemetry Channels [i_in] From [q_in] From1 Out1 Out2 i_in 1 0.214 In1 In2 In1 In2 In3 Out1 Out2 Channel Model Out1 Out2 Out3 Out4 Out5 Out5 QAM Receiver Original Subsystem Figure 1 – QAM system (System Generator model) fpt dbl cdeblk_indx1 fpt dbl rs_output fpt dbl dout_vld fpt dbl quad_sel fpt dbl start fpt dbl rs_input System Generator the Consultative Committee for Space Data Systems for telemetry channel coding specification (CCSDS 101.0 B-5). Introduction to the QAM System Design Example In our example, the overall QAM system starts with the transmitter. This subsystem accepts data from an input source, where forward error correction (FEC) is applied and an attached synchronization marker (ASM) is inserted into the data before modulation. The modulated data is then driven to the channel model, where inter-symbol interference, Doppler content, and additive white Gaussian noise are introduced into the signal. Finally, the receiver employs a 16- QAM demodulator that performs adaptive channel equalization and carrier recovery. The ASM is stripped from the demodulated data before applying error correction. A PicoBlaze microcontroller controls the Reed-Solomon decoder, maintains frame alignment of the received packets, and performs periodic adjustments of the demapping QAM-16 quadrant reference. Both the transmitter and the receiver are targeted to the FPGA, whereas the channel is a Simulink model used for simulation and verification. Although not all System Generator features are used in this design, it is a good example showing a combination of powerful features, using Xilinx blockset elements, legacy HDL code, a PicoBlaze processor, and hardware verification, resulting in a very elegant, efficient, and quick way to implement a complex design and qualify it in a single environment. Design Implementation with System Generator A System Generator design always starts and finishes with gateways to convert the Simulink double-precision data into a Xilinx fixed-point format. These gateways define the boundaries of your design; you can convert them into I/O ports for toplevel designs or an I/O interface to import into a higher-level system. Between these gateways, you must use blocks from the Xilinx library blockset or import your own code through the black box interface. The Xilinx blockset library comprises basic elements, math functions, DSP functions, communications blocks, control logic, and other useful elements. Each block is fully parameterizable, and a tight integration with the MATLAB workspace allows you to enter parameters based on complex equations or variables defined in the workspace. Equations such as this one: acc_nbits = ceil(log2(sum(abs(coef*2^coef_ width_bp)))) + data_width + 1 define the precision required for a filter as a function of the filter taps (coefficients), the number of taps, and the coefficient width. Because these are fixed at design time, it’s possible to tailor the hardware resources to Winter 2004 Xcell Journal 57 [i_in] [q_in] 0 DIGITAL SIGNAL PROCESSING
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