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GSRD Overview
The GSRD terminates IP-based transport protocols
such as TCP or UDP. It incorporates the
embedded PowerPC and RocketIO blocks
of the Virtex-II Pro device family, and is
delivered as an Embedded Development Kit
(EDK) reference system.
The reference system as described in
Xilinx Application Note XAPP536 leverages
a multi-port DDR SDRAM memory
controller to allocate memory bandwidth
between the PowerPC processor local bus
(PLB) interfaces and two data ports. Each
data port is attached to a direct memory
access (DMA) controller, allowing hardware
peripherals high-bandwidth access to
memory.
A MontaVista Linux port is available
for applications requiring an embedded operating
system, while a commercial standalone
TCP/IP stack from Treck is also available to
satisfy applications with the highest bandwidth
requirements.
System Architecture
Memory bandwidth is an important consideration
for high-performance networkattached
applications. Typically, external
DDR memory is shared between the processor
and one or more high-bandwidth peripherals
such as Gigabit Ethernet.
The four-port multi-port memory controller
(MPMC) efficiently divides the available
memory bandwidth between the
PowerPC’s instruction/data PLB interfaces
and a communications direct memory
access controller (CDMAC). The CDMAC
provides two bi-directional channels of
DMA that connect to peripherals through a
Xilinx standard LocalLink streaming interface.
The CDMAC implements data realignment
to support arbitrary alignment of
packet buffers in memory. A block diagram
of the system is shown in Figure 1.
The LocalLink Gigabit Ethernet MAC
(LLGMAC) peripheral incorporates the
UNH-tested Xilinx LogiCORE 1-Gigabit
Ethernet MAC to provide a 1 Gbps 1000-
BASE-X Ethernet interface to the reference
system. The LLGMAC implements checksum
offload on both the transmit and receive paths
for optimal TCP performance. Figure 2 is a
simplified block diagram of the peripheral.
FPGA Fabric
PPC405
DCR20PB
Dual GPIO
LEDs &
Pushbuttons
TX_DATA[31:0]
TX_REM[3:0]
TX_SOF_N
TX_SOP_N
TX_EOP_N
TX_EOF_N
TX_SRC_RDY_N
TX_DST_RDY_N
RX_DATA[31:0]
RX_REM[3:0]
RX_SOF_N
RX_SOP_N
RX_EOP_N
RX_EOF_N
RX_SRC_RDY_N
RX_DST_RDY_N
DCR_READ
DCR_WRITE
DCR Bus
DCR_WR_DBUS[0:31]
DCR_ABUS[0:9]
DCR_ACK
DCR_RD_DBUS[0:31]
DCR20PB
UART Lite
Winter 2004 Xcell Journal 15
ISPLB
DSPLB
Port 0 Port 1 Port 2 Port 3
PLB Interface
Port
XCVR
DB9
Multi Port Memory Controller
PLB Interface
Port
EMBEDDED SYSTEMS
DDR SDRAM
Communication
DMA Controller
RX0 TX0 RX1 TX1
RX TX
User Defined
LocalLink Peripheral
User Defined
Interface
RX
Checksum
Offload
TX
Checksum
Offload
LocalLink
GMAC Peripheral
Fiber Optics
*Can be customizable for other applications
Figure 1 – GSRD system block diagram
TX Peripheral
RX Peripheral
R
fa
Peripheral
Registers
CSUM
GEN
LocalLink Data
CSUM
FIFO
TX
FIFO
Xilinx LogiCORE
1-Gigabit
Ethernet MAC
CSUM
FIFO
RX
FIFO
Figure 2 – LocalLink Gigabit Ethernet MAC peripheral block diagram
CSUM
GEN
CSUM
Insert
RX Client Interface
TXP
TXN
RXP
RXN