Xcell Journal: The authoritative journal for programmable ... - Xilinx

Implementing 70 High-Speed
Channels with 9 FPGAs
Using nine Xilinx XC2VP7 circuits on a data concentrator card greatly
reduced costs and PCB design effort and increased board reliability.
by Jose C. Da Silva
Design Engineer
LIP (Laboratorio Instrumentacao e Particulas) – Lisbon
jc.silva@cern.ch
Adarsh Jain
Design Engineer
LIP (Laboratorio Instrumentacao e Particulas) – Lisbon
adarsh.jain@cern.ch
Implementing 70 high-speed differential
pairs on a 9U PCB using regular off-theshelf
deserializers can be a nightmare; highspeed
PCB design, noise, clock jitter, and
signal integrity are the main challenges.
Even the smallest deserializer packages
would occupy roughly two-thirds of a 9U
board, on which you would still need space
for the logic – configuration, memories,
access interfaces, and local control.
Our design concerns a data concentrator
card (DCC), part of a large high-energy
physics experiment at the European
Organization for Nuclear Research
(CERN) in Geneva. A very large particle
accelerator called the Large Hadron
Collider (LHC) is being constructed near
the Franco-Swiss border west of Geneva. A
number of experiments will be conducted
to observe and measure the various properties
of several existing, and possibly new,
fundamental particles.
Winter 2004 Xcell Journal 89