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System Generator for DSP The Xilinx System Generator tool suite was employed to implement a majority of the J.83 modulator design. System Generator is a visual dataflow design environment based on The MathWorks Simulink ® visual modeling tool set. This programming interface allows you to work at a suitable level of abstraction from the target hardware platform and use the same model – not only for simulation and verification but also for FPGA implementation. System Generator blocks are bit- and cycle-true behavioral models of FPGA Internet TV Broadcast DIGITAL SIGNAL PROCESSING This programming interface allows you to work at a suitable level of abstraction from the target hardware platform and use the same model. MPEG Framer F I F O MPEG F I Framer & F Randomizer O Web & Application Servers Receivers MPEG Encoders Remultiplexers (StatMuxes) RS Encoder RS Encoder Backplane (e.g. Fibre Channel) intellectual property components, or library elements. A library-based approach results in design cycle compression in addition to generating area-efficient highperformance circuits. Together with model features such as data-type propagation and the extensive virtual instruments that are part of the Simulink libraries, the environment facilitates rapid design space exploration, together with powerful mechanisms for model debugging. MATLAB ® scripts from The MathWorks programmatically generate custom VHDL and project files based on user-defined parameters. Cable Head-End Customer Premise Convolutional Interleaver Convolutional Interleaver Concatenated FEC CMTS Router Video Servers Modulators/ Transmitters Randomizer Byte to Symbol & Diff. Encoder F I F O Frame Sync Insertion & TCM Symbol Mapper F I F O F I F O Cable Modem Set Top Box Figure 1 – Cable network (J.83 modulator fits in the cable head-end modulator/transmitter block) Figure 2 – J.83 Annex B functional block diagram Concatenated FEC Figure 3 – J.83 Annex A/C functional block diagram RRC RRC J.83 in System Generator for DSP The J.83 specification defines the forward error correction (FEC) and baseband modulation with pulse-shaping characteristics. The J.83 Annex B FEC section (Figure 2) uses a concatenated coding technique with four processing layers, comprising an RS encoder, convolutional interleaver, randomizer followed by a frame sync insertion block, and trellis-coded modulation (TCM). The J.83 Annex A and Annex C (Figure 3) have identical FEC processing stages, comprising an RS encoder, convolutional interleaver, and a byte-to-symbol differential encoder, followed by a symbol mapper. The System Generator Xilinx library, or block set, is abundantly populated with IP that enables rapid design and simulation of such a system. The tokens required to construct the J.83 FEC section – as well as the filter blocks required to construct pulseshaping filters – are available within the library browser. The underlying circuit of each of these tokens is optimized in area and speed to suit the Xilinx family of devices. Each of these elements is conveniently customizable to be compatible with the precise specification of the J.83 standard. It is then a simple matter of using these customized library elements to build out the circuit required. For example, you can obtain the (204,188) RS encoder required for J.83 Annex A/C by using the Xilinx Reed Solomon encoder block, with the Code Specification parameter set to DVB. Similarly, the Xilinx interleaver deinterleaver block is directly used in the design, with the mode set to Interleaver and the Number of Branches and Length of Branches set to 12 and 17, respectively. This results in an exact match to the requirements of the interleaver in the J.83 A/C specification. Using the visual graphic means of design entry in System Generator, these blocks are easily connected to each other and to the control circuitry that is part of the design. 52 Xcell Journal Winter 2004
Figure 4 – J.83 Annex A/C modulator with scatter plot IP Simulation in Simulink It takes a lot of time to simulate and test the functionality of a complex system. You can use the same J.83 circuit built in System Generator for simulation and verification, as well as the FPGA implementation. Within the same environment, using Simulink for simulation, the design is stimulated with MPEG transport packets and the appropriate QAM, reset, synchronization, and other control inputs. As shown in Figure 4, this stimulus is shown in the block labeled “Stimuli.” The source, inter-packet gap, and burst nature of the MPEG transport packet may be chosen at random at the top level, allowing a test of the full suite of possibilities. Figure 4 also shows a discrete time scatter plot of the output of the baseband section of the modulator. Simulation of this complex system in an HDL simulator for a meaningful number of clock cycles (such that several frames of data may be processed) imposes a huge penalty in the time taken to complete a simulation. This makes it an impractical choice, but sometimes it is the only option when the design source is in an HDL format. This simulation time is drastically reduced when simulating the model in Simulink. What might take days to simulate in a gate-level simulator could be accomplished in a matter of hours. This savings in time is highly valuable – not only do you benefit from superior simulation speed in Simulink but you also reap the benefits of a shortened design cycle, allowing for overall rapid IP delivery. Single and Multi-Channel Designs The modulator is constructed out of two primary footprints or granularity: a single-channel implementation and a four-channel implementation. A block diagram of the four-channel granularity Annex B and A/C are shown in Figure 5 and Figure 6, respectively. Each instance of the singlechannel footprint provides for exactly one independent channel; the four-channel footprint, however, is optimized to efficiently support four channels at a time, using resourcesharing techniques. You select the granularity, and with that selection, make a trade-off between resource utilization and individual channel control. 1 1 1 1 8 8 MPEG Framer MPEG Framer MPEG Framer 1 1 Physical Interface Clock Mgmt 4x1b to 4x7b & FIFO Ext. Memory Memory Controller 28 1 ch RS 28 Inter- 28 Rando- 28 1 ch RS 1 ch RS leavermizer DIGITAL SIGNAL PROCESSING The trade-off is essentially in the area (resource) utilization; the optimized fourchannel group solution results in a very efficient and compact design requiring fewer FPGA resources. However, it imposes the restriction that the four channels must share the same controls. The singlechannel solution imposes no such restriction; the trade-off here is the linearly increasing FPGA resources used, which is directly proportional to the number of channels required. Multi-channel modulators are automatically constructed through the use of multiple copies (also referred to as groups) of the single- or four-channel implementation. For example, a four-channel modulator may be constructed with four copies of single-channel granularity or a single copy of the optimized 4-channel granularity design. Similarly, a 12-channel modulator may comprise 12 copies of the single-channel granularity design or 3 copies of the optimized 4-channel design. The ease of use is evident in that the Winter 2004 Xcell Journal 53 1 ch RS Controls (Frame, RST, Configuration & Channel Controls) Byte m Bits to 4 ch Conv. to 4-ch Byte RS Inter- m 4 4 32 32 32 Symbol Rando- & Enc. leaver 1 m mizer Sync (204, I=12, 2 FIFO 188) J=17 3 m 4 Clock Mgmt 4-ch Diff. Encode 7 7 TCM TCM Figure 5 – J.83 Annex B four-channel granularity design Controls (Frame, RST, Configuration, Channel) TDM Bus Symbol Mapper m = 4, 5, 6, 7, 8 for 16, 32, 64, 128, 256-QAM Figure 6 – J.83 Annex A/C four-channel granularity design I Q I1 Q1 I4 Q4 Prog. Controls Interleaver Select QAM Select Level Select TDM Bus I Q Async FIFO Async FIFO & 8 ch RRC � = 0.18 � = 0.12 TDM Bus I Q I1 Q1 I4 Q4 2 ch RRC Filter (a=0.15 or a=0.13) TDM Bus Q Prog. Controls QAM Select Annex A or C I
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System Communications Developing ap
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Forthcoming developments in future
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Why Prototype? The complexity assoc
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Xilinx Virtex-4 FPGAs http://www.xi
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TI Power Solutions: Power Behind Yo
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