Xcell Journal: The authoritative journal for programmable ... - Xilinx

PPC. This FIFO allows the relatively slow
66 MHz EPB bus to operate at full speed,
without having to implement low-level
hardware handshakes. A high-level handshake
is implemented by making the FIFO’s
fill level available for read-back by the PPC.
The PPC core can keep track internally
of the FIFO fill level and make decisions as
to whether to work on filling the FIFO or
perform other useful functions. The input
buffer also contains an auto-incrementing
register used to generate indirect addresses
for rapidly filling tables in other modules,
to keep the decoder’s I/O address range on
the EPB bus small.
The variable length (VL) decoder
decodes the Huffman-encoded block coefficients
according to MPEG-2 tables B-14
and B-15. State machines to traverse the
Huffman code trees and a look-up table to
extract run/level value pairs from the leafs
both fit into a single Virtex-II block RAM
configured as 1K deep x 16 bits wide.
We used some extra FPGA fabric for
shift registers to handle escape codes for
run/level values not included in the
Huffman code tables. The ISDSM block
handles the functions of inverting zigzag
scanning, dequantization, and scaling.
The iDCT was the easiest block to
design: it is included as a standard core in the
Xilinx ISE CORE Generator package.
The format converter assembles the Y,
Cb, and Cr sample blocks into slices in a
slice-assembly RAM buffer comprising 16
block RAMs. The slices are then scanned
out line by line and the lines are wrapped
EPBIn
EPBOut
Input
Buffer
in CCIR-656 start and end active video
(SAV/EAV) marker codes. We used an
address rotation technique so new blocks
can be assembled in the buffer as soon as a
single line is removed, allowing the pipeline
to run continuously without having to
double-buffer the slice assembly RAM.
Results
The original unoptimized MPEG-2 codec
chip external to the FPGA had a latency of
~1800 ms. Working with the codec chip
manufacturer, we reduced their latency to
45 ms. The I-frame decoder we developed
using the Xilinx FPGA and PPC has a
latency of less than 2 ms.
Conclusion
We saved a lot of time and effort using prebuilt
boards and IP in the development
process. If we had to develop the board, all
VL Decoder
Table Address
If we had to develop the board, all of
the associated software and all of the
IP that went into the low-latency decoder
and display system would have taken
years instead of months.
Controls
Inverse Scan
Dequantization
Saturation
Mismatch
(ISDSM)
Inverse DCT
Figure 5 – I-frame decoder block diagram
DIGITAL SIGNAL PROCESSING
of the associated software and all of the IP
that went into the low-latency decoder and
display system would have taken years
instead of months.
You can rapidly develop other video
processing functions, including:
• Other codecs – H.264, MPEG-4,
Motion JPEG2000
• Enhancement – linear and non-linear
filters, super-resolution, histogram
equalization/specification, de-convolution,
warping
• Stabilization and mosaicing
For more information on MPEG-2, read
the book, “MPEG Video Compression
Standard,” edited by Joan L. Mitchell et al.
And for more information on the
VigraWATCH system, visit www.titan.com,
keyword search “VigraWATCH.”
Format
Converter
To VigraWATCH
CCIR-656 Input
Winter 2004 Xcell Journal 77