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Xcell Journal: The authoritative journal for programmable ... - Xilinx

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Figure 1 – <strong>The</strong> Virtex-4 FPGA offers breakthrough DSP per<strong>for</strong>mance at new low-cost points.<br />

Even more revolutionary, Virtex-4 system<br />

designers need not employ the largest<br />

family member to achieve this per<strong>for</strong>mance,<br />

as has previously been the case.<br />

Virtex-4 FPGAs now deliver this signal<br />

processing capability in a medium-density<br />

device, providing you with as much as a<br />

staggering 10X increase in the available<br />

GMACs per dollar (see Figure 1). This dramatically<br />

extends production volumes<br />

where it makes economic sense to use an<br />

FPGA <strong>for</strong> per<strong>for</strong>mance-centric signal processing<br />

applications. <strong>The</strong> new DSP slices<br />

also dramatically reduce power consumption,<br />

allowing you to drive down both cost<br />

and power per channel.<br />

DSP to Logic Resources<br />

At the heart of the Virtex-4 FPGA’s signal<br />

processing resources are new highly integrated<br />

XtremeDSP slices, sometimes<br />

referred to as DSP48s (Figure 2).<br />

Depending on the family member, you<br />

can utilize as many as 512 XtremeDSP<br />

slices, each capable of providing 500 MHz<br />

throughput.<br />

Each slice contains a dedicated 2’s complement<br />

signed, 18 x 18 bit multiplier, and<br />

a three-input adder/subtracter with feedback<br />

<strong>for</strong> accumulation modes. <strong>The</strong> addition<br />

of a seven-bit op mode multiplexer<br />

allows you to dynamically configure the<br />

XtremeDSP slice <strong>for</strong> one of more than 40<br />

operating modes, such as addition, multi-<br />

plication, accumulation, MACC functions,<br />

MACC cascading, wide (48-bit)<br />

addition, and wide multiplexing.<br />

Configuration wizards in <strong>Xilinx</strong> ISE or<br />

System Generator <strong>for</strong> DSP allow you to<br />

simply apply the desired function.<br />

<strong>The</strong> addition of new XtremeDSP slices<br />

allows you to implement many such functions<br />

within the slice and without the need<br />

High Per<strong>for</strong>mance<br />

– 500 MHz, fully pipelined<br />

High Integration<br />

– 40+ DSP/arithmetic operation modes<br />

– Directly cascadeable<br />

Easy to implement<br />

– Software configuration wizards<br />

A (18-bit)<br />

B (18-bit)<br />

<strong>for</strong> external logic slices, which can thus be<br />

allocated to other tasks. XtremeDSP slices<br />

can also be cascaded directly without<br />

accessing logic fabric or any loss in speed.<br />

<strong>Xilinx</strong>’s new ASMBL architecture<br />

enables us to alter the mix of XtremeDSP<br />

slices and logic slices. <strong>The</strong> SX plat<strong>for</strong>m<br />

with in the Virtex-4 family offers the<br />

highest ratio of XtremeDSP slices to logic<br />

slices at one XtremeDSP slice <strong>for</strong> every<br />

108 logic slices. <strong>The</strong> SX plat<strong>for</strong>m is ideally<br />

suited <strong>for</strong> multiplier or MAC-intensive<br />

tasks such as software radios. <strong>The</strong> LX plat<strong>for</strong>m<br />

offers the highest ratio of logic to<br />

other features, and is suited <strong>for</strong> many traditional<br />

FPFA applications that may also<br />

require some DSP capability.<br />

Reduced Power Consumption<br />

In today’s infrastructure applications, driving<br />

down cost per channel is not the only<br />

goal diligently pursued. Wireless infrastructure<br />

manufacturers are under increasing<br />

pressure to stay within power limits<br />

imposed by governing telecom standards<br />

bodies. Power consumption is also becoming<br />

a key concern <strong>for</strong> some military applications,<br />

such as Joint Tactical Radio<br />

Systems radios.<br />

<strong>The</strong> integrated XtremeDSP slices on<br />

Virtex-4 FPGAs eliminate the need to use<br />

logic slices <strong>for</strong> many signal processing and<br />

arithmetic tasks, reducing the need <strong>for</strong><br />

power-consuming routing resources. Initial<br />

Winter 2004 <strong>Xcell</strong> <strong>Journal</strong> 61<br />

C (48-bit)<br />

Optional Pipeline Register/<br />

Routing Logic<br />

BCOUT PCOUT<br />

BCIN<br />

DIGITAL SIGNAL PROCESSING<br />

<strong>The</strong> integrated XtremeDSP slices on Virtex-4 FPGAs minimize the need<br />

to use logic slices <strong>for</strong> many signal processing and arithmetic tasks...<br />

Multiplier<br />

Optional Register<br />

Routing Logic<br />

Optional Pipeline Register/<br />

Routing Logic<br />

PCIN<br />

Figure 2 – New XtremeDSP slices feature 18 x 18 bit multiply, 48-bit accumulator<br />

P (48-bit)

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