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DIGITAL SIGNAL PROCESSING the filter specification. As you change coefficients, no modification will be required to the design, because the output precision will automatically be recalculated. This capability is only available with tools tightly integrated with MATLAB. The Xilinx blockset library will not always meet your needs, and some functions are better suited for HDL implementation, such as complex state machines or complex legacy code. The System Generator black box allows you to bring VHDL, Verilog, and EDIF netlists into a design. In the QAM design example, you can imagine replacing one of the FEC blocks (Reed-Solomon or Viterbi decoder) readily available from the Xilinx blockset library with your own HDL implementation through a black box. The black box behaves like other System Generator blocks – it is wired into designs, participates in simulations, and is compiled into hardware. When System Generator compiles a black box, it automatically wires the imported module and associated files into the surrounding netlist. System Generator simulates black boxes by automatically launching an HDL simulator, generating additional HDL as needed (analogous to an HDL test bench), compiling HDL, scheduling simulation events, and handling the exchange of data between the Simulink and the HDL simulator. This is called “HDL co-simulation.” At this point, you can also envision bringing MATLAB or C-code previously compiled with the appropriate MATLABto-gate and C-to-gate tools into the Xilinx black box. Simulation and Verification You can couple Simulink blocks with System Generator models to produce robust, flexible test bench environments. The convenience of this capability is that implementation and verification design phases can take place in the same environment. Such is the case with the QAM system design, where a mixture of Simulink and System Generator blocks were used to implement the design test bench. This allows you to verify the functionality of your design at any critical probing Figure 2 – Input (distorted channel) of the QAM demodulator Figure 3 – Output (constellation) of the QAM demodulator Figure 4 – System Generator GUI interface Figure 5 – Phase offset slider bar points in a format well understood by the DSP architect (such as sinewave or constellation). You can also automatically generate this exact same test bench and export it to an HDL simulation tool, in this case in a format well understood by the FPGA designer (binary waveform). Also automatically generated is “golden data” confirming similar functionality in the Simulink and HDL environments. In the QAM example, we chose to display the distorted channel on the output of the channel model (Figure 2) and the 16point constellation on the output of the QAM demodulator (Figure 3). Note that the automatic generation of the test bench and golden data saves an enormous amount of time over other design flows. Proceeding with the design implementation, you can now generate the netlist through the System Generator token (Figure 4). At the push of a button, you can decide to generate a VHDL netlist, which will then have to be synthesized and place and routed, or you can decide to go straight to a bitstream or even target a hardware demonstration board. Selecting hardware co-simulation makes it possible to incorporate a design running in an FPGA directly into a Simulink simulation. Hardware co-simulation compilation targets automatically create bitstreams and associate them with blocks. When the design is simulated in Simulink, results for the compiled portion are calculated in hardware. This allows the compiled portion to be tested in actual hardware, and can speed up simulation dramatically. In addition to supporting specialized interfaces such as the XtremeDSP kit, System Generator provides a generic interface that uses JTAG and the Parallel Cable IV to communicate with FPGA hardware. This takes advantage of the ubiquity of JTAG to extend System Generator’s hardware-in-the-simulation-loop capability to numerous other FPGA platforms. System Generator also allows you to run hardware co-simulation on your own development board. You can make design decisions and changes earlier in the design 58 Xcell Journal Winter 2004
process and accelerate the design cycle directly from the Simulink environment. Hardware Acceleration The complexity and size of the QAM system resulted in lengthy simulation times. To accelerate the simulation and confirm the functionality of this system, the transmitter and the receiver were downloaded to two separate FPGA boards and brought back into Simulink using System Generator’s hardware co-simulation feature. You are now simulating an entire system from Simulink, with 10 to 100 times faster simulation time, instantaneously validating the functionality in the FPGA. Interactively Control Hardware You can also go one step further by accessing the FPGA while running the simulation. In this QAM example, the amount of Doppler content introduced by the channel can be controlled interactively during simulation; a slider bar shifts the carrier phase of the modulated signal (Figure 5). A significant adjustment to the slider invariably causes the receiver to lose lock. Interactive control over Doppler provides a simple yet powerful way to test the functionality of the receiver’s control systems. Designers now have a simple way to simulate complex designs that require millions of samples that without hardware in the loop would take months to simulate. This, among other features, is something that only System Generator can offer. With other DSP design methodologies, you are required to verify designs in multiple design environments – a complicated process resulting in significantly slower simulation times. Conclusion System Generator is a mature tool that allows algorithm development, implementation, simulation, and verification in an environment understood by most designers. Although there are other design flows, no other tool offers features such as HDL co-simulation, hardware cosimulation, and integration with the ChipScope Pro tool and EDK, which are invaluable and only available in Xilinx System Generator for DSP. Virtex-II is a trademark of Xilinx, Inc. Virtex-II and Virtex-II Pro are trademarks of Xilinx, Inc. - Winter 2004 Xcell Journal 59 - TM DIGITAL SIGNAL PROCESSING TM TM
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ISSUE 51, WINTER 2004 XCELL JOURNAL
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EDITOR IN CHIEF Carlis Collins edit
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Page 96 and 97: Education Services Trims Your Learn
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Xilinx Virtex-4 FPGAs http://www.xi
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