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DIGITAL SIGNAL PROCESSING Developing a GSM Modem on a DSP/FPGA Architecture Using System Generator and Simulink, you can create a seamless simulation-to-implementation FPGA design flow. by Louis Belanger Product Development Manager Lyrtech Signal Processing, Inc. louis.belanger@lyrtech.com GSM (Global System for Mobile) is the most widely-used cellular phone technology. Having begun mostly as a European standard, it has spread throughout the world to become ubiquitous. GSM was one of the first digital cellular systems, and as such, represented another level of magnitude in terms of complexity, with support for growth features such as GPRS (General Packet Radio Service), which provides data capabilities to GSM phones. In this context, designing a GSM system is a complex task and could benefit from advanced design flow techniques where initial system simulation phases can be seamlessly carried over to the implementation phases. In this article, we’ll describe such a design flow for GSM development, starting from research and model simulation/implementation in The MathWorks MATLAB ® to FPGA implementation through simulation phases in The MathWorks Simulink® and Xilinx ® System Generator. Project Context Our implementation is in the general context of wireless application development examples to showcase our DSP/FPGA platforms. A previous project, the implementation of a SSB (single side band) AM radio (also with The MathWorks) featured a simpler analog radio and was showcased at Xilinx Programmable World 2003. We wanted to implement a much more complex radio, and so we selected the GSM digital cellular standard. In doing so, we are getting closer to our goal to design ever-more-complex wireless systems for our customers. We wanted to have a simplified system that still operates as a GSM system, while demonstrating a Model-Based (also known as system-level) Design flow. The target platform is our SignalMaster DSP-FPGA, with high-speed sampling boards to sample the intermediate frequency (IF) coming from a special-purpose radio frequency (RF) front end. We performed IF processing in the Xilinx Virtex-II FPGA and developed the design using System Generator. In a complementary manner, baseband processing implementation occurs in the DSP, using a similar Simulink design flow with the The MathWorks Real-Time Workshop C-code generator, Embedded Target for TI DSP toolbox, and LYRtech’s GSM DSP libraries. We designed protocol-oriented transactions using The MathWorks Stateflow, a 44 Xcell Journal Winter 2004
tool that allows the graphical design of states and transitions, as well as the production of associated code. This eventdriven code can run on the DSP itself or on a companion RISC processor. GSM Processing Figure 1 depicts a GSM physical channel. There are 124 200-kHz channels that are frequency multiplexed in a 25-MHz-wide RF spectrum, one for each downlink and uplink path. Figure 1 also shows in more detail how the “bursts” of each GSM channel are constructed. Basically, each burst is part of an 8-slot time division multiplex frame, forming a 200-kHz-wide spectrum. Each one has tail bits and an extended guard interval to avoid interference, as long as the mobile station (MS) is within 35 km of the base station (BS). Some fixed training-bit sequences allow synchronization between the MS and the BS. Using the GSM as a design example corresponds very well to our platform’s segmented architecture. The main uplink physical layer elements of a GSM speech and data transmission chain are shown in Figure 2. Figure 2 also illustrates how to partition the processing. We performed IF processing on the FPGA with functions such as polyphase DDC (digital down converter), DDS (direct digital synthesis), and GMSK (Gaussian Minimum Shift Keying) modulation. DSP-based baseband processing can tackle the tasks of encoding, encrypting, and interleaving, as well as burst building functions. Finally, communication protocol handling occurs at the RISC processor level (or in the DSP for simplified protocols, such as in our case). Simulink DSP Model The DSP section of the GSM model contains the following elements: • All higher level protocol layers • Baseband processing modules • Data transfer protocol for mapping data onto 32-bit frames, before sending to the FPGA through the parallel bus interface Figure 3 displays the DSP model, which contains the baseband processing block and Stateflow diagrams. This figure shows a combination of The MathWorks’ MAT- LAB off-the-shelf functions and target-specific library blocks. This is very typical of a Model-Based Design flow, in which target-specific block performance is compared with pure simulation blocks. At target compilation time, the associated DSP library of these last blocks can build the DSP code, providing very efficient code generation and performance. FPGA Processing Model-Based Design Figure 4 illustrates the main FPGA-based Simulink model for the base station. On the transmit side, the FPGA receives 148- GSM 25 MHz Bandwidth => 124 FDMA RF Channels 124 RF Channels 25 MHz Bandwidth 0 1 2 3 4 5 6 7 bit GSM frames from the DSP as input, modulates them to get a GMSK burst, and then frequency-shifts the resulting signal in the 70 MHz IF band through SSB modulation, using the Xilinx direct digital synthesizer (DDS) block. Two FDM transmit channels are simulated in this model. These two signals are then mixed together on the same physical channel and sent to the digital-to-analog converter (DAC); that block is located in the Signal I/O and Mixer subsystem. On the receiver side, signals feeding the FPGA come from the analog-to-digital converter (ADC). Because the digitized signal is 25 MHz wide and can contain as many as 124 GSM channels, channel selection is required. This is performed by a Type of Burst in GSM 1 TDMA channel => 1 burst Encrypted Bits Training Encrypted Bits 1 RF Channel, 200 KHz Bandwidth => 8 TDMA Channels Access Burst T: Tail bits G: Guard bits 1 burst => 156.25 symbols RX: 935-960 MHz X BPF A/D I Q LO Switched Voice Network IP Network (GPRS) If = 70 MHz 200 KHz Bandwidth Analog Section Winter 2004 Xcell Journal 45 T T T Encrypted Fixed Bits Synchronization T Synchronization Encrypted T X DDS Polyphase Filters Control Protocol Engine Baseband RISC or DSP Protocol Processing DIGITAL SIGNAL PROCESSING Figure 1 – GSM FDM, TDM, and burst structure DSP Section Viterbi Decode Deinterleaving Encrypted G T G Normal Burst T G Frequency-Correction Burst GMSK Demod T G Synchronization Burst RF IF and TDM Processing FPGA Section Burst Processing Burst Processing Speech Decoder Figure 2 – Partitioning of the GSM processing between the FPGA, the DSP, and a RISC processor
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