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DIGITAL SIGNAL PROCESSING
Virtex-4 FPGAs bring a new revolutionary era in the XtremeDSP
initiative that provides you with economic incentives to use FPGAs
and get your design to market faster than ever before.
power estimates show that XtremeDSP
slices consume only 57 µW/MMAC, representing
one-seventh the power for an
equivalent function implemented using
Virtex-II Pro FPGAs. Although not the
ultimate goal, this reduction in power goes
some way in addressing the power concerns
of infrastructure equipment providers.
Another way to reduce system power
consumption in such applications is to use
the embedded processor capabilities available
on the FX platform. You have the
option to trade gates for processor cycles for
sequential control tasks using FX platform
devices. Examples of such implementations
include software communication architectures
or real-time operating systems.
High Compute Density Using SRL16s
Shift Register Logic (SRL16) is a unique
feature in Xilinx FPGAs. A popular feature
for increasing compute density in multichannel
implementations, SRL16s are
included in all Virtex-4 platforms.
To demonstrate SRL16 usage, let’s take
a look at a simple Reed-Solomon encoder
example. Implementing a single-channel
Reed-Solomon encoder in a Virtex-4
device consumes 56 logic slices. For a 16-
GF Multiplier
GF Adder
One
SRL16
channel implementation, one approach
would be to replicate this 16 times, resulting
in a consumption of 16 x 56 slices.
Figure 3 shows another implementation
of the 16-channel solution using SRL16s.
This consumes only 86 logic slices, representing
only 10% of the 16X replicated
version. SRL16s can substantially pack
more signal processing into a smaller area,
allowing you to potentially target a much
smaller device than is possible with other
FPGA architectures.
Serial/Parallel Connectivity
In addition to embedded processors, the
FX platform also includes 3.125 Gbps
multi-gigabit transceivers that are particularly
suited for interfacing to other DSP
processors. One such example is highspeed
serial connectivity using the serial
RapidIO interface, which is gaining
momentum with DSP vendors. With 1
Mbps LVDS interfaces for interfacing to
high-speed A/D converters and a host of
DRAM and SRAM memory interfaces for
hooking up to frame buffers, the Virtex-4
family is an ideal platform for interfacing
to other DSP devices that will form part of
the system data flow.
Message
Gate
Figure 3 – Efficient 16-channel Reed-Solomon encoder using SRL 16
Virtex-4 DSP Design Solutions
The Virtex-4 family includes a beefed-up
set of DSP design resources.
• System Generator for DSP allows
you to model your design in The
MathWorks Simulink ® and, through
powerful capabilities like hardwarein-the-loop,
verify and debug that
design from the same environment.
System Generator also includes a
new block that allows you to instantiate
an XtremeDSP slice and configure
it for one of its many operating
modes.
• Hardware-in-the-loop is supported for
any Virtex-4 development environment
with a JTAG header. Other new
capabilities introduced in System
Generator 6.3 include the ability to
generate VHDL or Verilog netlists.
• The Xilinx DSP library now supports
Virtex-4 FPGAs, allowing you to
develop designs faster.
• A range of services are now available
as you implement your DSP design
onto Virtex-4 FPGAs. These include
DSP design services, education classes,
and platinum/technical support.
Conclusion
FPGA-based DSP has always been associated
with high performance when hundreds
of GMACs/s rates are needed.
Virtex-4 FPGAs bring a new revolutionary
era in the XtremeDSP initiative that provides
you with economic incentives to use
FPGAs and get your design to market
faster than ever before.
To understand how to use the new
XtremeDSP slices in your next design,
attend the Virtex-4 session in the DSP
track at Programmable World 2004, or
watch the demo-on-demand that will follow
the event at www.xilinx.com/dsp/.
62 Xcell Journal Winter 2004
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