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through simple cable connections supporting more than 2 Gbps data rates. The SMT148 leverages the Xilinx Virtex-II Pro block RAM configuration to generate FIFOs for the RocketIO transceivers, add-on modules communication ports, and a high-speed bus, as well as the embedded PowerPC code. The single highspeed bus allows parallel data transfer to and from a wide range of high-speed ADC/DAC modules. µc1 µc2 EMBEDDED SYSTEMS CP0 CP1 CP2 CP3 CP4 CP5 CP6 CP7 ComPort IF 0 µc IF1 µc IF2 TIM1 TIM2 TIM3 TIM4 ComPort IF 1 ComPort IF 2 ComPort IF 3 Data rates on this port are in excess of 100 MHz (400 Mbps), and are useful for transferring sampled 16-bit I and Q. Processing data streams can take place either in the embedded PowerPC in the Virtex-II Pro device or throughout an array of other add-on Virtex-II Pro FPGAbased modules with embedded PowerPC. The FPGA on the SMT148 carrier card is connected to many different devices and therefore has many internal interfaces that allow it to exchange data or commands with the external world. All interfaces are reset at power on when applying a manual reset. Figure 4 shows the interconnections between the digital modules inside the FPGA. ComPort IF 4 Switch Fabric When we designed the SMT148, we understood that one of the many challenges OEMs would face in developing JTRS-compliant platforms was the availability of interchangeable and networked processing nodes. The availability of processing nodes aims to meet the expandability and scalability requirements in complex waveform applications. The SMT148 meets this availability challenge with a network of daughter sites that ComPort IF 5 ComPort IF 6 DAC IF ADC IF LED IF RSL IF SHB IF RS485 IF DAC ADC LED RSL SHB RS485 ComPort IF 7 Watchdog Timer 1 Watchdog Timer 2 Watchdog Timer 3 Watchdog Timer 4 McBSP en/dis 1 McBSP en/dis 2 McBSP en/dis 3 McBSP en/dis 4 RESET TIMs you can use for additional resources such as signal processors, reconfigurable computing modules, and Sundance’s large family of addon modules. These add-on modules include a variety of embedded system options such as reconfigurable modules with tightly coupled Virtex-II Pro FPGAs and DSPs, digital and analog converters, data conversions, transceivers, and I/Os of all types. Designed for Developers Powered by an external supply, the SMT148 platform has an impressive topology that accepts input signals from various sources through a network of multi-pin connectors. High-speed I/O channels support the additional nodes in a network topology neatly harmonized to the Xilinx architecture. Fully interconnected and configurable through their communication ports, these add-on sites are also connected to the embedded Virtex-II Pro FPGA. The availability of a network of add-on sites removes the main expandability restrictions often associated with other platforms, and offers the OEMs a highly compact design and development tool. More importantly, this scalable system architecture makes the SMT148 a perfect development platform with which to resolve the many issues related to the implementation of multiple radio functionalities in a single environment. These can be addressed as multiple software modules running on Sundance’s reconfigurable hardware platform. IP Cores Sundance takes advantage of the high-performance DSP acceleration capabilities and flexible connectivity that the Virtex-II Pro FPGA provides by supporting developers with a family of software tools and IP cores. The SMT148 I/O flexibility enables you to rapidly investigate and experiment with features of the Virtex-II Pro FPGA as well as those of developed IP cores from Sundance. These include multi-tap complex filters, Viterbi decoders, encoders, a complete transmitter, QAM mapper, multiphase pulse shaping filter, multi-phase cascaded integrator comb (CIC) interpolation filter with a fixed interpolation rate, multiphase numerical-controlled oscillator (NCO), and multi-phase digital mixer. Conclusion Developing, testing, and implementing SDR IP cores is simplified with the Sundance SMT148 platform. You can now focus on developing additional IPs without worrying about peripheral processing or I/O devices, as these are simply off-the-shelf add-on IP blocks. For more information, please visit www.sundance.com. 28 Xcell Journal Winter 2004 McBSP IF Global Bus IF1 Global Bus IF2 Global Bus IF3 Global Bus IF4 To/From LVDS Drivers/Receivers Figure 3 – Interconnections diagram of the digital modules inside the SMT148 R E S E T GB1 GB2 GB3 GB4
Implementing High-Speed Optical Burst Switching with Virtex-II Pro FPGAs The OBS protocol tested successfully with the Virtex-II Pro FPGA. EMBEDDED SYSTEMS by Sam Sanyal Solutions Marketing Manager Xilinx, Inc. sam.sanyal@xilinx.com Mrugendra Singhai Research Engineer MCNC Research and Development Institute msinghai@anr.mcnc.org Imagine a telecom network where an optical network can be set up and torn down in an instant without any human intervention. An optical burst switching (OBS) protocol at work at the Microsystems Computer North Carolina Research Development Institute (MCNC-RDI) in Research Triangle Park, North Carolina, does just that. OBS combines the best features of optical circuit switching and optical packet switching. An OBS network can switch variable-sized data bursts instead of individual data packets. In an OBS network, transmission of data bursts can begin even before those bursts are completely formed. These features of the OBS networks are similar to an optical circuit-switched network. Like an optical packet-switching network, an OBS network can dynamically control system resources, assigning wavelengths of optical fiber to individual data bursts only when that user needs to transmit data. Unlike some optical packetswitched networks, an OBS network does not require optical buffers. Winter 2004 Xcell Journal 29
Page 1 and 2: ISSUE 51, WINTER 2004 XCELL JOURNAL
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I would like to see Xilinx System G
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Early Access: The Designer’s Edge
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Agilent Signal 250 Khz - 3Ghz Agile
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We picked [9 Xilinx Virtex-II Pro d
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LIN Bus - A Cost-Effective Alternat
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Automotive Cost Speed Network Per N
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Education Services Trims Your Learn
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Board of Education The UNM FPGA pro
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FPGAs Ensure Flexible and Adaptable
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Why Prototype? The complexity assoc
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TI Power Solutions: Power Behind Yo
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