Xcell Journal: The authoritative journal for programmable ... - Xilinx
Xcell Journal: The authoritative journal for programmable ... - Xilinx
Xcell Journal: The authoritative journal for programmable ... - Xilinx
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Figure 1 – DSP Co-Processing Design Kit hardware plat<strong>for</strong>m<br />
DSP Co-Processing Design Kit<br />
<strong>The</strong> DSP Co-Processing Design Kit features<br />
a Virtex-II Pro evaluation board,<br />
shown in Figure 1. This board contains a<br />
<strong>Xilinx</strong> XC2VP7-FF896 FPGA, eight SMA<br />
connectors <strong>for</strong> high-speed I/O, on-board<br />
DDR SDRAM (64 MB), up to 30 LVDS<br />
pairs, user I/O switches/LEDs, and several<br />
expansion connectors.<br />
Two of the expansion connectors are<br />
compatible with the TI adaptor daughtercard<br />
(shown in Figure 2) and can connect<br />
to TI DSPs. Example designs show how to<br />
interface directly with the TI processor<br />
using the <strong>Xilinx</strong> EDK toolset and a direct<br />
memory interface approach.<br />
A co-processing-oriented application<br />
can use the hardware plat<strong>for</strong>m, demonstration<br />
designs, and included tools as a great<br />
starting point <strong>for</strong> prototype design and<br />
algorithm development. DSP applications<br />
are often very difficult to simulate in software,<br />
so the ability to quickly create a hardware/firmware/software<br />
plat<strong>for</strong>m can cut<br />
development time significantly. Using the<br />
co-simulation tools available in the <strong>Xilinx</strong><br />
tool suite through <strong>The</strong> MathWorks<br />
Simulink and the target hardware is one<br />
technique that can dramatically reduce<br />
design time.<br />
Additionally, deciding what portions of<br />
the algorithm to process in the DSP and<br />
which portion to process in the FPGA can<br />
often best be done with a trial-and-error<br />
approach, using real hardware to quickly<br />
evaluate the per<strong>for</strong>mance of various<br />
options. For example, the number of data<br />
streams that can be pre-processed by an<br />
FPGA be<strong>for</strong>e post-processing by a DSP will<br />
depend on many factors – the “burstiness”<br />
of the incoming data, the “accept”<br />
response rate of the DSP, the size of the<br />
buffer memories, the bandwidth of the system<br />
bus, and the amount of pre-processing<br />
allocated to the FPGA. <strong>The</strong>se are all difficult<br />
decisions to make without doing<br />
some detailed hardware prototype-based<br />
analysis.<br />
Figure 2 – DSP processor adaptor module<br />
DIGITAL SIGNAL PROCESSING<br />
<strong>The</strong> DSP Co-Processing Design Kit also<br />
includes the following software tools, as<br />
evaluation versions, from the <strong>Xilinx</strong><br />
XtremeDSP Software Evaluation CD<br />
Kit: <strong>Xilinx</strong> ISE 6.2 Foundation,<br />
ChipScope Pro, <strong>Xilinx</strong> System Generator<br />
<strong>for</strong> ISE 6.2, <strong>The</strong> MathWorks MATLAB,<br />
and Simulink.<br />
Video DSP Design Kit<br />
<strong>The</strong> Video DSP Design Kit targets simple<br />
DSP-oriented video applications in the<br />
industrial security, consumer, and automotive<br />
markets. Algorithms <strong>for</strong> video processing<br />
like image recognition, video encode,<br />
video decode, and video image enhancement<br />
are all very difficult to prototype and<br />
evaluate without actual hardware on which<br />
to run the software or firmware. Using a<br />
DSP Design Kit, with some simple video<br />
capabilities, can make it much easier and<br />
quicker to prototype and evaluate various<br />
algorithms and architecture alternatives.<br />
<strong>The</strong> Video DSP Design Kit features a<br />
<strong>Xilinx</strong> Spartan-3 XC3S400-FG456 or<br />
XC3S1500-FG456 FPGA, Plat<strong>for</strong>m Flash<br />
configuration PROM, expansion connectors,<br />
32-bit PCI edge connector, 10/100<br />
Ethernet port, video DAC, RS-232 console,<br />
PS2 keyboard and mouse ports, simple<br />
analog I/O, 1 MB SRAM, 256 Kb<br />
serial EEPROM, and a variety of user<br />
switches and LEDs.<br />
Winter 2004 <strong>Xcell</strong> <strong>Journal</strong> 49