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Functional % of Run-Time
Blocks Total Cycles
mv_search.c 67.31 %
block.c 8.19 %
refbuf.c 6.95 %
macroblock.c 3.48 %
rdopt.c 3.37 %
biariencode.c 3.21 %
cabac.c 2.98 %
memcpy.asm* 2.91 %
abs.c* 0.57 %
image.c 0.54 %
rdopt_coding_state.c 0.46 %
loopFilter.c 0.03 %
Table 1 – H.264/AVC encoder
complexity profile by files
However, computation complexity
alone does not determine if a functional
module should be mapped to hardware or
remain in software. To evaluate the viability
of software and hardware partitioning of the
H.264/AVC coding standard implementation
on a platform that consists of a mixture
of FPGAs, programmable DSPs, or generalpurpose
host processors, we need to look at
a number of architectural issues that influence
the overall design decision.
• Data locality. In a synchronous design,
the ability to access memory in a particular
order and granularity while minimizing
the number of clock cycles due
to latency, bus contention, alignment,
DMA transfer rate, and the types of
memory used (such as ZBT memory,
SDRAM, and SRAM) is very important.
The data locality issue is primarily
dictated by the physical interfaces
between the data unit and the arithmetic
unit (or the processing engine).
• Data parallelism. Most signal processing
algorithms operate on data that is
highly parallelizable (such as FIR filtering).
Single instruction multiple data
(SIMD) and vector processors are particularly
efficient for data that can be
parallelized or made into a vector format
(or long data width).
FPGA fabric exploits this by providing
a large amount of block RAM to support
numerous very high aggregate
bandwidth requirements. In the new
Xilinx Virtex-4 SX device family, the
amount of block RAM matches closely
with the number of Xtreme DSP
slices (SX25 – 128 block RAM, 128
DSP slices; SX35 – 192 block RAM,
192 DSP slices; SX55 – 320 block
RAM, 512 DSP slices).
• Signal processing algorithm parallelism.
In a typical programmable DSP
or a general-purpose processor, signal
processing algorithm parallelism is
often referred to as instruction level
parallelism (ILP). A very long instruction
word (VLIW) processor is an
example of such a machine that
exploits ILP by grouping multiple
instructions (ADD, MULT, and BRA)
to be executed in a single cycle. A
heavily pipelined execution unit in the
processor is also an excellent example
of hardware that exploits the parallelism.
Modern programmable DSPs
have adopted this architecture (including
the Texas Instruments
TMS320C64x).
However, not all algorithms can
exploit such parallelism. Recursive
algorithms like IIR filtering, variablelength
coding (VLC) in MPEG1/2/4,
context-adaptive variable length coding
(CAVLC), and context-adaptive binary
arithmetic coding (CABAC) in
H.264/AVC are particularly sub-optimal
and inefficient when mapped to
these programmable DSPs. This is
because data recursion prevents ILP
from being used effectively. Instead,
dedicated hardware engines can be
built efficiently in the FPGA fabric.
• Computational complexity.
Programmable DSP is bounded in
computational complexity, as measured
by the clock rate of the processor.
Signal processing algorithms implemented
in the FPGA fabric are typically
computationally intensive. Some
examples of these are the sum of
DIGITAL SIGNAL PROCESSING
absolute difference (SAD) engine in
motion estimation and video scaling.
By mapping these modules onto the
FPGA fabric, the host processor or the
programmable DSP has the extra cycles
for other algorithms. Furthermore,
FPGAs can have multiple clock
domains in the fabric, so selective hardware
blocks can thus have separate
clock speeds based on their computational
requirements.
• Theoretic optimality in quality. Any
theoretic optimal solution based on
the rate-distortion curve can be
achieved if and only if the complexity
is unbounded. In a programmable
DSP or general-purpose processor, the
computational complexity is always
bounded by the clock cycles available.
FPGAs, on the other hand, offer much
more flexibility by exploiting data and
algorithm parallelism by means of
multiple instantiations of the hardware
engines, or increased use of block
RAM and register banks in the fabric.
A programmable DSP or general-purpose
processor is often limited by the
number of instruction issues per cycle,
the level of pipeline in the execution
unit, or the maximum data width to
fully feed the execution units. Video
quality is often compromised as a result
of the limited cycles available per task
in a programmable DSP, whereas hardware
resources are fully allocated in
FPGA fabric (three-step vs. full-search
motion estimation).
Implementing Functional Modules onto FPGAs
Figure 1 shows the overall H.264/AVC
macroblock level encoder with major functional
blocks and data flows defined. One
of the primary successes of the H.264/AVC
standard is its ability to predict the values
of the content of a picture to be encoded by
exploiting the pixel redundancy in different
ways and directions not exploited previously
in other standards. Unfortunately, when
comparing to previous standards, this
increases the complexity and memory
access bandwidth approximately four-fold.
Winter 2004 Xcell Journal 41