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DIGITAL SIGNAL PROCESSING
Xilinx black box is in a model file, and the
VHDL code to configure it resides in the
folder in which the model file is saved, then
the configuration wizard for the black box
will automatically generate an .m file to
describe the functionality of the black box.
With System Generator 3.1, you can configure
the black box manually.
Figure 6 – Example model demonstrating
clock enable probe use
Figure 7 – Scope output from
clock enable probe example
A problem exists when generating the .m
file through the wizard. The configuration
wizard for the black box cannot realize multiple
entities in the .vhd file. The VHDL
file bbrx.vhd contained multiple entities
because of inefficient VHDL code generation
through Xilinx StateCAD. Thus, you
must manually manipulate the code to
reduce it to one entity. You can then use the
Figure 8 – Propagation of enable signal through delay blocks
modified VHDL code in conjunction with
the Xilinx black box wizard, creating a
block shown like that in Figure 5.
System Generator 6.1 Features
The Fast Fourier Transform (FFT) implementation
through configuration of a
Xilinx black box block with M-file and
VHDL wrapper file had problems in the
past with execution in Simulink. These
problems arose from the fact that System
Generator did not appear to allow for multiple
sampling rates (for instance, a clock
and its respective down-sampled version).
This problem has since been alleviated
with the addition of a clock enable probe system
generator block. This block lets you
effectively up- and down-sample a clock rate
such that multiple clock rates are allowed
within the same model. Figures 6 and 7 illustrate
an example of the clock enable probe.
DSP Circuitry Synchronization
Synchronous design goes hand in hand
with the development of DSP circuitry.
Therefore, it is important to be able to realize
synchronous design in the high-level
abstraction that System Generator provides.
Note that Xilinx delay blocks are used
for “delaying” enable signals for a duration
that matches computation effort time. You
can use the output of this delay as an effective
“output enable,” as shown in Figure 8.
These delays are of such importance that
before enabling the second block in a
chain, you want to make sure the first
block has completed its computation.
Exploring “FFT_power.mdl” demonstrates
that latency requirements increase
when the precision of the
inputs and output of the
multiplier block increase.
Thus, the delays need to be
modified when greater
computational effort and
thus greater time requirements
in terms of Xilinx
block latency result from
overall design changes.
You could add greater
flexibility to the Xilinx
blockset with the addition
of extra input parameters to
some of the blocks in the set. For instance,
the count-limited counter does not offer a
count-to value as a possible input parameter.
Therefore, dynamic configuration of
the counter threshold is unrealizable.
Output enables allow one stage to signify
it is complete, and thus for the next
stage to start. Currently, most of the blocks
in the blockset do not provide signals
telling you when the block is finished its
computation. This would be helpful in the
handshaking for several Xilinx blocks.
However, you can realize output enable
signals and counter threshold input signals
by generating a VHDL file using the
Xilinx Core Generator tool, and then
configuring a Xilinx black box. But this
requires more time from the designer and
greater engineering effort as well.
We have to consider flexibility (the
addition of output enables and other input
parameters) to offer dynamic configuration
of blocks versus a trade-off in maintaining
the abstraction desired by DSP designers
lacking strong digital design skills. It is
therefore important to consider these ideas
in future versions of System Generator.
Conclusion
A custom logic design may seem like a
daunting task, but with the flexibility
offered by Xilinx System Generator, it is
quite achievable. Xilinx MCode and black
box block configuration offer viable solutions
for implementing custom logic.
System Generator is a very powerful and
abstract tool, but we would like to see greater
flexibility in terms of achieving synchronous
design within System Generator.
80 Xcell Journal Winter 2004