Xcell Journal: The authoritative journal for programmable ... - Xilinx

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DIGITAL SIGNAL PROCESSING New XtremeDSP Slices Deliver As Much As 10X More GMACs Per Dollar Virtex-4 FPGAs offer breakthrough DSP performance at the lowest cost. by Narinder Lall Senior Manager – DSP Product and Solutions Marketing Xilinx, Inc. narinder.lall@xilinx.com Xilinx ® Virtex Series FPGAs have been the preferred choice for high-performance signal processing and DSP co-processing in many digital communications and video/imaging applications. With algorithmic complexity on the rise, the pervasive need for flexibility, and increasing downward pressures on price/power per channel, designers often face tough tradeoffs and difficult choices to employ either FPGA- or ASIC-centric systems for challenging signal processing applications. New XtremeDSP slices on the Virtex-4 device family extend FPGA signal processing capability beyond 256 GMACs, which represents DSP performance two times greater than previous generation Virtex-II Pro FPGAs. 60 Xcell Journal Winter 2004
Figure 1 – The Virtex-4 FPGA offers breakthrough DSP performance at new low-cost points. Even more revolutionary, Virtex-4 system designers need not employ the largest family member to achieve this performance, as has previously been the case. Virtex-4 FPGAs now deliver this signal processing capability in a medium-density device, providing you with as much as a staggering 10X increase in the available GMACs per dollar (see Figure 1). This dramatically extends production volumes where it makes economic sense to use an FPGA for performance-centric signal processing applications. The new DSP slices also dramatically reduce power consumption, allowing you to drive down both cost and power per channel. DSP to Logic Resources At the heart of the Virtex-4 FPGA’s signal processing resources are new highly integrated XtremeDSP slices, sometimes referred to as DSP48s (Figure 2). Depending on the family member, you can utilize as many as 512 XtremeDSP slices, each capable of providing 500 MHz throughput. Each slice contains a dedicated 2’s complement signed, 18 x 18 bit multiplier, and a three-input adder/subtracter with feedback for accumulation modes. The addition of a seven-bit op mode multiplexer allows you to dynamically configure the XtremeDSP slice for one of more than 40 operating modes, such as addition, multi- plication, accumulation, MACC functions, MACC cascading, wide (48-bit) addition, and wide multiplexing. Configuration wizards in Xilinx ISE or System Generator for DSP allow you to simply apply the desired function. The addition of new XtremeDSP slices allows you to implement many such functions within the slice and without the need High Performance – 500 MHz, fully pipelined High Integration – 40+ DSP/arithmetic operation modes – Directly cascadeable Easy to implement – Software configuration wizards A (18-bit) B (18-bit) for external logic slices, which can thus be allocated to other tasks. XtremeDSP slices can also be cascaded directly without accessing logic fabric or any loss in speed. Xilinx’s new ASMBL architecture enables us to alter the mix of XtremeDSP slices and logic slices. The SX platform with in the Virtex-4 family offers the highest ratio of XtremeDSP slices to logic slices at one XtremeDSP slice for every 108 logic slices. The SX platform is ideally suited for multiplier or MAC-intensive tasks such as software radios. The LX platform offers the highest ratio of logic to other features, and is suited for many traditional FPFA applications that may also require some DSP capability. Reduced Power Consumption In today’s infrastructure applications, driving down cost per channel is not the only goal diligently pursued. Wireless infrastructure manufacturers are under increasing pressure to stay within power limits imposed by governing telecom standards bodies. Power consumption is also becoming a key concern for some military applications, such as Joint Tactical Radio Systems radios. The integrated XtremeDSP slices on Virtex-4 FPGAs eliminate the need to use logic slices for many signal processing and arithmetic tasks, reducing the need for power-consuming routing resources. Initial Winter 2004 Xcell Journal 61 C (48-bit) Optional Pipeline Register/ Routing Logic BCOUT PCOUT BCIN DIGITAL SIGNAL PROCESSING The integrated XtremeDSP slices on Virtex-4 FPGAs minimize the need to use logic slices for many signal processing and arithmetic tasks... Multiplier Optional Register Routing Logic Optional Pipeline Register/ Routing Logic PCIN Figure 2 – New XtremeDSP slices feature 18 x 18 bit multiply, 48-bit accumulator P (48-bit)
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ISSUE 51, WINTER 2004 XCELL JOURNAL
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EDITOR IN CHIEF Carlis Collins edit
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Xilinx Virtex-4 FPGAs http://www.xi
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