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DIGITAL SIGNAL PROCESSING
only requirement is for you to specify the
parameters; the multiple instantiations of
the basic footprints and the required connections
between them are automatically
generated, leaving you with a core design
tailored to those exact specifications.
Usage
The Xilinx J.83 modulator implementation
is available as a module that plugs into
Xilinx System Generator for DSP, or as a
netlist that may be directly referenced by
another design. The design of the J.83 core
in System Generator allows for generation
with a simple push button solution.
Through a GUI constructed in the familiar
Simulink environment, the core provides
you with a convenient means of supplying
design specifics such as the granularity
desired, the number of channels required,
and clock rates, as shown in Figure 7.
Figure 7 – J.83 Annex B
generator GUI screenshot
During parameterization and generation,
the core is automatically configured to the
specifications and deposited into the target
directory. Along with the netlist, the core
also includes behavioral and timing simulation
script files (.do) for Mentor Graphics ®
ModelSim and an ISE Project Navigator
project file (.npl). From this point on, you
can bring the core into the ISE Project
Navigator environment for synthesis, place
and route, and bitstream generation.
Resource Sharing
The Xilinx FPGA implementation of the
J.83 modulator specification capitalizes
on a particular architectural feature to
construct efficient multi-channel implementations:
the shift register logic 16
(SRL16) primitive, found in Virtex-II,
Virtex-II Pro, and Spartan-3 devices.
You can think of SRL16 as a series concatenation
of 16 flip-flops with a programmable
tap point. This unique aspect
of Xilinx FPGAs is extremely powerful for
building very efficient time-division multiplexed
(TDM) hardware that you can
use, for example, to process multiple
channels of data.
Because they run the design at a faster
rate, TDM processing structures save
resources. This has been notably exploited
during the design of an optimized multichannel
group of modulators. For example,
in the design of the optimized
four-channel granularity of a group, all
channels share a common control structure
in the MPEG framer, RS encoder,
interleaver, randomizer, and TCM. As the
interleaver controls are shared, the data
path into and out of the interleaver effectively
becomes wider.
Number
of Channels
Resource Utilization
Using the resource sharing techniques
we’ve described thus far, you can realize significant
savings in the implementation of
modulators constructed out of optimized
four-channel granularity designs compared
to the equivalent constructed out of singlechannel
granularity designs.
Table 1 and Table 2 show a comparison
of the resources used in the design of various
sizes of J.83 modulators using single- and
four-channel granularity footprints. They
also show the resources used to implement 4,
8, and 12 channels of J.83 Annex B and J.83
Annex A/C solutions on a Spartan-3 device.
Although Table 1 details the resources
on an implementation that does not contain
the optional root-raised cosine filter,
the details in Table 2 are specific to an
implementation that contains the option.
Using the 12-channel case as an example,
the scales are favorably tipped towards a
four-channel granularity implementation
of the J.83 Annex B and J.83 Annex A/C,
as the savings achieved are significant.
J.83 Annex B J.83 Annex A/C
Slices/BRAM/External Memory Slices/BRAM
One Channel Four Channel One Channel Four Channel
Granularity Granularity Granularity Granularity
4 3372/8/1 1866/2/1 1574/4 1049/3
8 6764/16/2 3644/4/1 3130/8 2088/6
12 10049/24/2 5405/6/1 4683/12 3304/9
Number
of Channels
Table 1 – Resource utilization comparison between one- and four-channel granularity
J.83 Annex A/B/C designs without RRC (Spartan-3 FPGAs)
J.83 Annex B J.83 Annex A/C
Slices/BRAM/External Memory Slices/BRAM
One Channel Four Channel One Channel Four Channel
Granularity Granularity Granularity Granularity
4 8014/20/1 3748/7/1 4829/8 2444/4
8 16024/40/2 7402/14/1 9661/16 4877/8
12 23924/60/2 11057/21/1 14449/24 7483/12
Table 2 – Resource utilization comparison between one- and four-channel granularity
J.83 annex A/B/C designs with RRC (Spartan-3 FPGAs)
54 Xcell Journal Winter 2004