Xcell Journal: The authoritative journal for programmable ... - Xilinx

I would like to see Xilinx System
Generator offer more flexibility (with the
addition of output enables and other input
parameters) to offer dynamic configuration
of blocks. This flexibility comes at the
expense of maintaining abstraction if you
would prefer not to immerse yourself in the
details of digital VLSI design.
Using a Xilinx MCode Block
If you are implementing a straightforward
logic algorithm, configuring the MCode
block is an easier solution than building the
logic together through Xilinx blockset
logic. Let’s describe an example implementation
of custom logic; in this case, a
function [tone_q, noise_q, filter_finish] =
switch_cir(d, BBRX_Start, tone_bin, BBRX_End, enable, BBRX_Finish)
if(BBRX_Finish==false)
if((d>=BBRX_Start) &(d =tone_bin-7)&(d=tone_bin+8)&( d