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DESIGN FLOW WITH DIMEtalk Connect Algorithms Import algorithms as HDL code or Xilinx compatible netlist and connect into the DIMEtalk network Synthesis Synthesize whole design using standard synthesis tools Figure 2 – DIMEtalk design flow We are not suggesting that DIMEtalk networks should completely replace other types of data networks. However, within FPGAs and going between FPGAs on the same card, a low-resource, easy-to-implement network such as DIMEtalk makes sense – as demonstrated by the resource usage shown in Figure 1. DIMEtalk is intended to be used alongside other data network and backplane Figure 3 – Hardware for example system Network Definition Define DIMEtalk network for FPGA computing system using DIMEtalk software tool Assign to Devices Assign network to FPGAs and use Device Editor to drag and drop port signals to the FPGA UCF I/O signals Implementation Implement design using standard implementation tools Develop Algorithms Develop rest of application using standard design entry flows (HDL, System Generator, AccelFPGA, Handel-C, etc.) Generate Code DIMEtalk automatically generates HDL code and user constraints files for complete design Runtime Appl ication operating in runtime, using DIMEtalk API functions to communicate across DIMEtalk network types – that’s why the edge components are so important. The edges enable you to use low-resource DIMEtalk networks where it is right to do so and interface directly to other protocols off-card. Using DIMEtalk DIMEtalk is designed to make life easier for developers to deploy applications on an FPGA computing platform. The intuitive Xilinx Virtex-II 2V6000 FPGA VME Interface Xilinx Virtex-II 2V6000 FPGA Xilinx Virtex-II 2V6000 FPGA design flow shown in Figure 2 enables easy network implementation and you can use the design-entry tool of your choice for algorithm blocks. The stages of the design flow are: • Network Definition – conceptually design the network to provide communications links and interface points to algorithms as required across the FPGAs • Develop Algorithms – use HDL or other tools to develop algorithm blocks using HDL or other design flows connected to the interface nodes of the DIMEtalk network • Connect Algorithms – connect the completed algorithm blocks to the network; at this stage, the network and application are functionally complete • Assign to Devices – assign the whole design to FPGAs using a drag-anddrop feature • Code Generation – automatic code generation for design • Synthesis – using standard synthesis tools • Implementation – using the Xilinx ISE software tool flow Xilinx Virtex-II Pro 2VP50 FPGA SRAM SRAM SRAM SRAM SRAM SRAM Xilinx Virtex-II 2V6000 FPGA Figure 4 – Hardware block diagram for example system 106 Xcell Journal Winter 2004 SRAM SRAM Gigabit Ethernet
Forthcoming developments in future releases of DIMEtalk will include additional interface support and links directly into algorithm development tools... Application Architecture Example Let’s look at DIMEtalk in an application context. The easiest approach is a very highlevel one to avoid getting caught up in the details of a potential system – the focus being on the overall architecture rather than lowlevel functionality. A typical application might include the following: • VME form-factor • Multiple high-density platform FPGAs • High-speed external analog interfaces • High-speed synchronous SRAM memory • Gigabit Ethernet interface This relatively complex hardware configuration is shown in Figures 3 and 4. In this case, the system comprises commercial offthe-shelf hardware products. From a functional perspective, the algorithm processing blocks that would perform the function of this application reside within the FPGAs. VME Interface FPGA FPGA FPGA N N B R N E Edge R B Bridge N Router Node N FPGA N N B R B B R N B B A E R You can develop these algorithm blocks using the design entry flow of your choice, including HDL, commercial IP cores, and high-level languages and tools. An example DIMEtalk network for this system is shown conceptually and in the DIMEtalk software tool in Figures 5 and 6. The network spans across all five FPGAs in the system, with router and bridge elements in place as appropriate to enable the network to operate. Each FPGA has algorithm blocks(s) associated with it – these are connected to the network at user nodes. The user node type and location can be defined to fit your application requirements. In this example, the network is also connected through a DIMEtalk edge to the VMEbus host interface on the system – enabling direct data communications from the host to specific algorithm blocks inside the FPGAs. What is clear from this example is the value DIMEtalk adds to the system. You N N R B N B R N Brightly colored blocks represent algorithms Figure 5 – DIMEtalk network shown for example system can take an off-the-shelf system along with your algorithm blocks and rapidly connect all of these together and to the VMEbus. Conclusion Using DIMEtalk, you can efficiently implement the systems communications infrastructure required for FPGA computing applications. The generated network is flexible and provides a complete communications solution to connect together algorithm blocks, interfaces, backplane links, and host system. This type of infrastructure would have taken significantly longer to implement using traditional methods. Forthcoming developments in future releases of DIMEtalk will include additional interface support and links directly into algorithm development tools, making application development even easier. For further information about DIMEtalk, visit www.nallatech.com/ dimetalk/. Figure 6 – Screenshot of DIMEtalk network portion for example system Winter 2004 Xcell Journal 107
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ISSUE 51, WINTER 2004 XCELL JOURNAL
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