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European Journal of Scientific Research ISSN 1450-216X Vol.20 No.4 (2008), pp.759-771 © EuroJournals Publishing, Inc. 2008 http://www.eurojournals.com/ejsr.htm Design Space Exploration of Regular NoC Architectures: A Multi-Objective Evolutionary Algorithm Approach Rabindra Ku. Jena Faculty of IT, Institute of Management Technology, Nagpur, India E-mail: rk_jena2@rediffmail.com Musbah M. Aqel Faculty of IT, Middle East University for Graduate Studies Ammam, Jordan E-mail: Aqelm06@yahoo.com Gopal K. Sharma Department of IT ABV-Indian Institute of Information Technology & Management, Gwalior, India E-mail: gksharma@yahoo.com Prabhat K. Mahanti Department of CSAS, University of New Brunswick, Saint John, Canada E-mail: pkmahanti@yahoo.co.in Abstract In this paper, we address the problem of topological mapping of intellectual properties (IPs) on the tile of a mesh-based NoC to minimize energy and maximum bandwidth requirement. As the stated problem is NP-hard in nature, we proposed a heuristic technique based on multi-objective genetic algorithm to obtain an optimal approximation of the pareto-optimal. We have considered “many-many” mapping between switch and cores (IPs) instead of “one-one” mapping. The evaluation performed on randomly generated benchmarks and a real application (a M-JPEG encoder), showed the efficiency, accuracy and scalability of our proposed approach. Keywords: NoC optimization, energy, performance, system level synthesis, Genetic algorithm. 1. Introduction Network on Chip (NoC) has been proposed as a solution for the communication challenges like propagation delays, scalability, infeasibility of synchronous communication etc. in a nano scale regime (Zitzler and Thiele, 1999; Hu and Marculescu, 2003). To meet these challenges under the strong timeto-market pressure, it is essential to increase the reusability of components and system architectures in a plug and play fashion (Hu and Marculescu, 2003). Simultaneously, the volume of data and control traffic among the cores grows. So, it is essential to address the communication-architecture synthesis
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