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Design Space Exploration of Regular NoC Architectures: A Multi-Objective Evolutionary Algorithm Approach 770 Figure 10: Maximum Link Bandwidth and Energy comparisons for M-JPEG. Normalized Values 1 0.8 0.6 0.4 0.2 0 MGA PBB MGAP Energy Max. Link Bandwidth Performance Matrices Figure 11: M-JPEG Encoder performance using NSGA-II. Figure 12: ‘Many-Many’ Vs ‘One-One’ performance comparison. 8. Conclusion In this paper we have proposed a model for topological mapping of IPs/cores in a mesh-based NoC architecture with many- many mappings between core to switches. The approach uses heuristics based on multi-objective genetic algorithms (NSGA-II) to explore the mapping space and find the pareto mappings that optimize Maximum link bandwidth and performance and power consumption. The experiments carried out with randomly generated benchmarks and a real application (M-JPEG encoder system) confirms the efficiency, accuracy and scalability of the proposed approach. Future developments will mainly address the definition of more efficient genetic operators to improve the precision and convergence speed of the algorithm Evaluation will also be made of the possibility of
771 Rabindra Ku. Jena, Musbah M. Aqel, Gopal K. Sharma and Prabhat K. Mahanti optimizing mapping by acting on other architectural parameters such as routing strategies, switch buffer sizes, etc. References [1] A. D. Pimentel, S. Polstra, F. Terpstra, A. W. van Halderen, J. E. Coffland, and L. O.Hertzberger (2002) Towards efficient design space exploration of heterogeneous embedded media systems. E. Deprettere, J. Teich, and S. Vassiliadis, editors, Embedded Processor Design Challenges: Systems, Architectures, Modeling, and Simulation, volume 2268 of LNCS, Springer-Verlag, pp.7–73. [2] C. A. Coello, D. A. Van Veldhuizen, and G. B. Lamont (2002) Evolutionary Algorithms for Solving Multi-Objective Problems. Kluwer Academic Publishers, New York. [3] C. J. Glass and L. M. Ni (1992) The Turn Model for Adaptive Routing, Proc.19 th Ann. Int’l Symp. Computer Architecture, pp. 278-287. [4] Deb, K. (2002) Multi-Objective Optimization using Evolutionary Algorithms, John Wiley and Sons Ltd, pp. 245-253. [5] E. Zitzler and L. Thiele (1999) Multi-objective evolutionary algorithms: A comparative case study and the strength pareto approach, IEEE Transactions on Evolutionary Computation, 4(3), pp.257–271. [6] J. Hu and R. Marculescu (2003) Energy-aware mapping for tile-based NoC architectures under performance constraints, Asia & South Pacific Design Automation Conference. [7] J. Hu and R. Marculescu (2003) Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures, Proc. DATE’03, pp. 688-693. [8] Jena R. K., Sharma, G.K, (2006) A multi-objective Optimization Model for Energy and Performance Aware Synthesis of NoC architecture, Proceedings of IP/SoC, Decmber 6-7, pp 477-482. [9] K. Lahiri, A. Raghunathan, and S. Dey (2000) Efficient Exploration of the SoC Communication Architecture Design Space, Proc. IEEE/ACM ICCAD’00, pp. 424-430. [10] K. Srinivasan and Karam S. Chatha (2005) ISIS: A Genetic Algorithm based Technique for Custom On-Chip Interconnection Network Synthesis, Proceedings of the 18 th International Conference on VLSI Design (VLSID’05). [11] Luca Benini and Giovanni De Micheli (2002) Networks on Chips: A New SoC Paradigm, IEEE Computer, pp. 70–78. [12] M. R. Garey and D. S. Johnson (1979) Intractability: a guide to the theory of NP-completeness, Freeman and Company. [13] N. Banerjee, P. Vellanki, and K. S. Chatha (2004) A power and performance model for network-on-chip architectures, Design, Automation and Test in Europe, pp. 1250–1255. [14] S. Kumar et al. (2002) A Network on Chip Architecture and Design Methodology, Proc. ISVLSI’02, April 2002, pp. 105-112. [15] S. Murali and G. D. Micheli (2004) Bandwidth-constrained mapping of cores onto NoC architectures, Design, Automation, and Test, Europe IEEE Computer Society, pp. 896–901. [16] T. Lei and S. Kumar (2003) A two-step genetic algorithm for mapping task graphs to a network on chip architecture, Euro micro Symposium on Digital Systems Design, Sept. 1–6. [17] T. T. Ye, L. Benini, and G. D. Micheli (2002) Analysis of Power Consumption on Switch Fabrics in Network Routers, Proc. DAC’02, pp.524-529. [18] William J. Dally and Brian Towles (2002) Route Packet, Not Wires: On-Chip Interconnection Networks, Proceedings of DAC.
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