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Numonyx <strong>Wireless</strong> <strong>Flash</strong> <strong>Memory</strong> (<strong>W30</strong>)<br />
Figure 12: Synchronous 4-Word Burst Read Operation Waveform<br />
R12<br />
Notes:<br />
1. Section 14.2, “First Access Latency Count (RCR[13:11])” on page 80 describes how to insert clock<br />
cycles during the initial access.<br />
2. WAIT (shown asserted; RCR[10] = 0) can be configured to assert either during, or one data cycle before, valid data.<br />
November 2007 Datasheet<br />
Order Number: 290702-13 35<br />
R11<br />
R13
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