Numonyxâ„¢ Wireless Flash Memory (W30)

Numonyx Wireless Flash Memory (W30)
Table 19: Bus Cycle Definitions
Operation Command
Protection
Bus
Cycles
Protection Program 2 Write PA C0h Write PA PD
Lock Protection Program 2 Write LPA C0h Write LPA FFFDh
Configuration
Notes:
Set Configuration
Register
2 Write CD 60h Write CD 03h
1. First-cycle command addresses must be the same as the target address of the operation. Examples:
—The first-cycle address for the Read Identifier command must be the same as the Identification code address (IA).
—The first-cycle address for the Word Program command must be the same as the word address (WA) to be
programmed.
—The first-cycle address for the Erase/Program Suspend command must be the same as the address within the block
to be suspended.
XX= Any valid address within the flash device.
IA= Identification code address.
BA= Block Address. Any address within a specific block.
LPA= The Lock Protection Address is obtained from the CFI (through the Read Query command). The W30 flash
memory device family LPA is at 0080h.
PA= User programmable 4-word protection address.
PnA= Any address within a specific partition.
PBA= Partition Base Address. The first address of a particular partition.
QA= Query code address.
WA= Word address of memory location to be written.
2. SRD= Status register data.
WD= Data to be written at location WA.
IC= Identifier code data.
PD= User programmable 4-word protection data.
QD= Query code data on D[7:0].
CD= Configuration register code data presented on flash device addresses A[15:0]. A[MAX:16] address bits can
select any partition. See Table 27, “Read Configuration Register Definitions” on page 79 for
configuration
register bits descriptions.
3. Do not use commands other than those shown above. Other commands are reserved by Numonyx for future flash
device implementations.
9.3 Command Sequencing
First Bus Cycle Second Bus Cycle
Oper Addr 1
Data 2,3
Oper Addr 1
Data 2,3
When issuing a 2-cycle write sequence to the flash device, a read operation can occur
between the two write cycles. The setup phase of a 2-cycle write sequence places the
addressed partition into read-status mode, so if the same partition is read before the
second confirm write cycle is issued, status register data is returned. Reads from other
partitions, however, can return actual array data, if the addressed partition is already in
read-array mode. Figure 25 and Figure 26 illustrate these two conditions.
Figure 25: Normal Write and Read Cycles
Address [A]
WE# [W]
OE# [G]
Data [Q]
Partition A Partition A Partition A
20h D0h FFh
Block Erase Setup Block Erase Conf irm Read Array
November 2007 Datasheet
Order Number: 290702-13 53