Numonyxâ„¢ Wireless Flash Memory (W30)

More documents

Recommendations

Info

Figure 36: Protection Register Locking 13.3 VPP Protection 0x88 0x85 0x84 0x81 0x80 User-Programmable Intel Factory-Programmed PR Lock Register 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Numonyx Wireless Flash Memory (W30) (W30) The Product Name provides in-system program and erase at V PPL . For factory programming, the W30 flash memory device also includes a low-cost, backwardcompatible 12 V programming feature.(See “Factory Programming” on page 60.) The EFP feature can also be used to greatly improve factory program performance, as explained in Section 11.3, “Enhanced Factory Program (EFP)” on page 61. In addition to flexible block locking, holding the V PP programming voltage low can provide hardware write protection of all flash-device blocks. If V PP is below V PPLK , program or erase operations result in an error displayed in SR[3]. (See Figure 37.) Figure 37: Examples of VPP Power Supply Configurations System supply 12 V supply ≤ 10K Ω • 12 V fast programming • Absolute write protection with V PP ≤ V PPLK System supply (Note 1) 12 V supply VCC VPP VCC VPP • Low voltage and 12 V fast programming System supply Prot# (logic signal) VPP • Low-voltage programming • Absolute write protection via logic signal System supply • Low-voltage programming Note: If the V CC supply can sink adequate current, you can use an appropriately valued resistor. Datasheet November 2007 78 Order Number: 290702-13 VCC VCC VPP
Numonyx Wireless Flash Memory (W30) 14.0 Set Read Configuration Register The Set Read Configuration Register (RCR) command sets the burst order, frequency configuration, burst length, and other parameters. A two-bus cycle command sequence initiates this operation. The read configuration register data is placed on the lower 16 bits of the address bus (A[15:0]) during both bus cycles. 1. The Set Read Configuration Register command is written, along with the configuration data (on the address bus). 2. A second write confirms the operation and again presents the read configuration register data on the address bus. 3. The read configuration register data is latched on the rising edge of ADV#, CE#, or WE# (whichever occurs first). This command functions independently of the applied V PP voltage. After executing this command, the flash device returns to read-array mode. To examine the contents of the read configuration register, write the Read Identifier command and then read location 05h. (See Table 27 and Table 28.) Table 27: Read Configuration Register Definitions Read Mod e Res’d First Access Latency Count WAIT Polarit y Data Outpu t Config WAI T Confi g Burs t Seq Cloc k Confi g November 2007 Datasheet Order Number: 290702-13 79 Res’ d Res’ d Burs t Wra p Burst Length RM R LC2 LC1 LC0 WP DOC WC BS CC R R BW BL2 BL1 BL0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Table 28: Read Configuration Register Descriptions (Sheet 1 of 2) Bit Name Description1 Notes 15 RM Read Mode 0 = Synchronous Burst Reads Enabled 1 = Asynchronous Reads Enabled (Default) 14 R Reserved 5 13-11 10 9 8 7 6 LC[2:0] First Access Latency Count WP WAIT Signal Polarity DOC Data Output Configuration WC WAIT Configuration BS Burst Sequence CC Clock Configuration 001 = Reserved 010 = Code 2 011 = Code 3 0 = WAIT signal is asserted low 1 = WAIT signal is asserted high (Default) 0 = Hold Data for One Clock 1 = Hold Data for Two Clock (Default) 100 = Code 4 101 = Code 5 111 = Reserved (Default) 0 = WAIT Asserted During Delay 1 = WAIT Asserted One Data Cycle before Delay (Default) 1 = Linear Burst Order (Default) 0 = Burst Starts and Data Output on Falling Clock Edge 1 = Burst Starts and Data Output on Rising Clock Edge (Default) 5 R Reserved 5 4 R Reserved 5 2,6 6 3 6 6
Page 2 and 3:
Legal Lines and Disclaimers INFORMA
Page 4 and 5:
Numonyx Wireless Flash Memory (W30)
Page 6 and 7:
Date of Revision 11/17/03 -008 Vers
Page 8 and 9:
• RWE - Read-While-Erase • RWW
Page 10 and 11:
Page 12 and 13:
Table 2: Top Parameter Memory Map M
Page 14 and 15:
Figure 2: 32Mb, 64Mb and 128Mb QUAD
Page 16 and 17:
Figure 4: 32Mb VF BGA Package Drawi
Page 18 and 19:
4.0 Ballout and Signal Descriptions
Page 20 and 21:
4.2 Signal Descriptions Numonyx Wir
Page 22 and 23:
Table 6: Signal Descriptions - QUAD
Page 24 and 25:
Page 26 and 27:
6.0 Electrical Specifications 6.1 D
Page 28 and 29: 7.0 AC Characteristics 7.1 Read Ope
Page 30 and 31: Table 12: Read Operations - 180 nm
Page 32 and 33: Figure 9: Latched Asynchronous Read
Page 34 and 35: Figure 11: Single Synchronous Read-
Page 36 and 37: Numonyx Wireless Flash Memory (W30)
Page 38 and 39: Figure 15: Burst Suspend CLK Addres
Page 40 and 41: Figure 16: Write Operations Wavefor
Page 42 and 43: Figure 19: Synchronous Read to Writ
Page 44 and 45: 8.0 Power and Reset Specifications
Page 46 and 47: 8.6 Reset Specifications Table 15:
Page 48 and 49: 9.0 Flash Device Operations Numonyx
Page 50 and 51: 9.1.4 Reset 9.1.5 Write Numonyx Wir
Page 52 and 53: Table 18: Command Codes and Descrip
Page 54 and 55: Figure 26: Interleaving a 2-Cycle W
Page 56 and 57: Table 20: Flash Device Identificati
Page 58 and 59: 10.5 Clear Status Register Numonyx
Page 60 and 61: Figure 28: Word Program Flowchart S
Page 62 and 63: 11.3.2 Setup Numonyx Wireless Flash
Page 64 and 65: Figure 29: Enhanced Factory Program
Page 72 and 73: Figure 33: Block Locking State Diag
Page 76 and 77: Table 26: Simultaneous Operations A
Page 80 and 81: Table 28: Read Configuration Regist
Page 86 and 87: Appendix A Write State Machine Numo
Page 90 and 91: B.2 Query Structure Overview Numony
Page 92 and 93: Table 37: System Interface Informat
Page 94 and 95: B.6 Numonyx-Specific Extended Query
Page 96 and 97: Table 43: Partition Region 1 Inform
Page 98 and 99: Table 45: Partition and Erase-Block
Page 100 and 101: Table 47: 48F Type Stacked Componen
Page 102: Table 51: Parameter / Mux Configura
show all

Numonyxâ„¢ Wireless Flash Memory (W30)

Create successful ePaper yourself

Delete template?

Save as template?