Numonyxâ„¢ Wireless Flash Memory (W30)

Table 28: Read Configuration Register Descriptions (Sheet 2 of 2)
14.1 Read Mode (RCR[15])
Numonyx Wireless Flash Memory (W30) (W30)
All partitions support two high-performance read configurations and RCR[15] sets the
read configuration to one of these modes:
• synchronous burst mode
• asynchronous page mode (default)
Status register, query, and identifier modes support only asynchronous and singlesynchronous
read operations.
14.2 First Access Latency Count (RCR[13:11])
The First Access Latency Count (RCR[13:11]) configuration tells the flash device how
many clocks must elapse from ADV# de-assertion (V IH ) before driving the first data
word onto its data pins. The input clock frequency determines this value. See Table 27,
“Read Configuration Register Definitions” on page 79 for latency values.
Figure 38 shows data output latency from ADV# assertion for different latencies. Refer
to Section 14.2.1, “Latency Count Settings” on page 81 for Latency Code Settings.
Note: Other First Access Latency Configuration settings are reserved.
)
Bit Name Description1 Notes
3
2-0
BW
Burst Wrap
BL[2:0]
Burst Length
0 = Wrap bursts within burst length set by CR[2:0]
1 = Don’t wrap accesses within burst length set by CR[2:0].(Default)
001 = 4-Word Burst
010 = 8-Word Burst
011 = 16-Word Burst (Available on the 130 nm lithography)
111 = Continuous Burst (Default)
Notes:
1. Undocumented combinations of bits are reserved by Numonyx for future implementations.
2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register
and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0].
3. Data is not ready when WAIT is asserted.
4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words.
5. Set all reserved Read Configuration Register bits to zero.
6. Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010),
data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported.
Figure 38: First Access Latency Configuration
CLK [C]
Address [A]
ADV# [V]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
D[15:0] [Q]
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Address
Code 2
Code 3
Code 4
Code 5
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Output
Datasheet November 2007
80 Order Number: 290702-13
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4