Numonyxâ„¢ Wireless Flash Memory (W30)

Numonyx Wireless Flash Memory (W30) (W30)
In either case, if WAIT is deasserted, then data is ready and valid. WAIT is asserted
during asynchronous page mode reads.
14.4 WAIT Signal Function
CE# = V IH
CE# = V IL
The WAIT signal indicates data valid when the flash device is operating in synchronous
mode (RCR[15]=0), and when addressing a partition that is currently in read-array
mode. The WAIT signal is deasserted only when data is valid on the bus.
• When the flash device is operating in synchronous non-read-array mode, such as
read status, read ID, or read query, WAIT is set to an asserted state, as determined
by RCR[10]. See Figure 14, “WAIT Signal in Synchronous Non-Read Array
Operation Waveform” on page 37.
• When the flash device is operating in asynchronous page mode or asynchronous
single word read mode, WAIT is set to an asserted state, as determined by
RCR[10]. See Figure 10, “Page-Mode Read Operation Waveform” on page 33, and
Figure 8, “Asynchronous Read Operation Waveform” on page 31.
From a system perspective, the WAIT signal is in the asserted state (based on
RCR[10]) when the flash device is operating in synchronous non-read-array mode
(such as Read ID, Read Query, or Read Status), or if the flash device is operating in
asynchronous mode (RCR[15]=1). In these cases, the system software must ignore
(mask) the WAIT signal, because WAIT does not convey any useful information about
the validity of what is appearing on the data bus.
CONDITION WAIT
14.5 Data Hold (RCR[9])
Tri-State
Active
OE# No-Effect
Synchronous Array Read Active
Synchronous Non-Array Read Asserted
All Asynchronous Read and all Write Asserted
The Data Output Configuration (DOC) bit (RCR[9]) determines whether a data word
remains valid on the data bus for one or two clock cycles. The minimum data set-up
time on the processor, and the flash memory clock-to-data output delay, determine
whether one or two clocks are needed.
• A DOC set at 1-clock data hold corresponds to a 1-clock data cycle.
• A DOC set at 2-clock data hold corresponds to a 2-clock data cycle.
The setting of this configuration bit depends on the system and CPU characteristics. For
clarification, see Figure 41. The following is a method for determining this configuration
setting.
To set the flash device at 1-clock data hold for subsequent reads, the following
condition must be satisfied:
t CHQV (ns) + t DATA (ns) < One CLK Period (ns)
As an example, use a clock frequency of 54 MHz and a clock period of 25 ns. Assume
the data output hold time is one clock. Apply this data to the formula above for the
subsequent reads:
Datasheet November 2007
82 Order Number: 290702-13