Numonyxâ„¢ Wireless Flash Memory (W30)

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Table 28: Read Configuration Register Descriptions (Sheet 2 of 2) 14.1 Read Mode (RCR[15]) Numonyx Wireless Flash Memory (W30) (W30) All partitions support two high-performance read configurations and RCR[15] sets the read configuration to one of these modes: • synchronous burst mode • asynchronous page mode (default) Status register, query, and identifier modes support only asynchronous and singlesynchronous read operations. 14.2 First Access Latency Count (RCR[13:11]) The First Access Latency Count (RCR[13:11]) configuration tells the flash device how many clocks must elapse from ADV# de-assertion (V IH ) before driving the first data word onto its data pins. The input clock frequency determines this value. See Table 27, “Read Configuration Register Definitions” on page 79 for latency values. Figure 38 shows data output latency from ADV# assertion for different latencies. Refer to Section 14.2.1, “Latency Count Settings” on page 81 for Latency Code Settings. Note: Other First Access Latency Configuration settings are reserved. ) Bit Name Description1 Notes 3 2-0 BW Burst Wrap BL[2:0] Burst Length 0 = Wrap bursts within burst length set by CR[2:0] 1 = Don’t wrap accesses within burst length set by CR[2:0].(Default) 001 = 4-Word Burst 010 = 8-Word Burst 011 = 16-Word Burst (Available on the 130 nm lithography) 111 = Continuous Burst (Default) Notes: 1. Undocumented combinations of bits are reserved by Numonyx for future implementations. 2. Synchronous and page read mode configurations affect reads from main blocks and parameter blocks. Status Register and configuration reads support single read cycles. RCR[15]=1 disables the configuration set by RCR[14:0]. 3. Data is not ready when WAIT is asserted. 4. Set the synchronous burst length. In asynchronous page mode, the burst length equals four words. 5. Set all reserved Read Configuration Register bits to zero. 6. Setting the Read Configuration Register for synchronous burst-mode with a latency count of 2 (RCR[13:11] = 010), data hold for 2 clocks (RCR[9] = 1), and WAIT asserted one data cycle before delay (RCR[8] =1) is not supported. Figure 38: First Access Latency Configuration CLK [C] Address [A] ADV# [V] D[15:0] [Q] D[15:0] [Q] D[15:0] [Q] D[15:0] [Q] Valid Address Code 2 Code 3 Code 4 Code 5 Valid Output Datasheet November 2007 80 Order Number: 290702-13 Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output Valid Output 4
Numonyx Wireless Flash Memory (W30) Figure 39: Word Boundary Note: The 16-word boundary is the end of the flash device sense word-line. 14.2.1 Latency Count Settings Table 29: Latency Count Settings Word 0 - 3 Word 4 - 7 Word 8 - B Word C - F 0 1 2 3 4 5 6 7 8 9 A B C D E F t AVQV /t CHQV (85ns/22ns) t AVQV /t CHQV (70ns/20ns) t AVQV /t CHQV (90ns/22ns) Unit Latency Count Settings 2 3, 4, 5 2, 3, 4, 5 2 3, 4, 5 Frequency < 31 < 33 < 40 < 29 < 33 MHz Figure 40: Data Output with LC Setting at Code 3 CLK (C) CE# (E) ADV# (V) A MAX-0 (A) DQ 15-0 (D/Q) 4 Word Boundary t ADD-DELAY 14.3 WAIT Signal Polarity (RCR[10]) 16 Word Boundary • If the WT bit is cleared (RCR[10]=0), then WAIT is configured to be asserted low. A 0 on the WAIT signal indicates that data is not ready and the data bus contains invalid data. • Conversely, if RCR[10] is set, then WAIT is asserted high. November 2007 Datasheet Order Number: 290702-13 81 R103 High Z t DATA 0st 1nd 2rd 3th 4th Code 3 Valid Address Valid Output Valid Output
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Legal Lines and Disclaimers INFORMA
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Numonyx Wireless Flash Memory (W30)
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Date of Revision 11/17/03 -008 Vers
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• RWE - Read-While-Erase • RWW
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Table 2: Top Parameter Memory Map M
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Figure 2: 32Mb, 64Mb and 128Mb QUAD
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Figure 4: 32Mb VF BGA Package Drawi
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4.0 Ballout and Signal Descriptions
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4.2 Signal Descriptions Numonyx Wir
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Table 6: Signal Descriptions - QUAD
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6.0 Electrical Specifications 6.1 D
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7.0 AC Characteristics 7.1 Read Ope
Page 30 and 31: Table 12: Read Operations - 180 nm
Page 32 and 33: Figure 9: Latched Asynchronous Read
Page 34 and 35: Figure 11: Single Synchronous Read-
Page 36 and 37: Numonyx Wireless Flash Memory (W30)
Page 38 and 39: Figure 15: Burst Suspend CLK Addres
Page 40 and 41: Figure 16: Write Operations Wavefor
Page 42 and 43: Figure 19: Synchronous Read to Writ
Page 44 and 45: 8.0 Power and Reset Specifications
Page 46 and 47: 8.6 Reset Specifications Table 15:
Page 48 and 49: 9.0 Flash Device Operations Numonyx
Page 50 and 51: 9.1.4 Reset 9.1.5 Write Numonyx Wir
Page 52 and 53: Table 18: Command Codes and Descrip
Page 54 and 55: Figure 26: Interleaving a 2-Cycle W
Page 56 and 57: Table 20: Flash Device Identificati
Page 58 and 59: 10.5 Clear Status Register Numonyx
Page 60 and 61: Figure 28: Word Program Flowchart S
Page 62 and 63: 11.3.2 Setup Numonyx Wireless Flash
Page 64 and 65: Figure 29: Enhanced Factory Program
Page 72 and 73: Figure 33: Block Locking State Diag
Page 76 and 77: Table 26: Simultaneous Operations A
Page 78 and 79: Figure 36: Protection Register Lock
Page 86 and 87: Appendix A Write State Machine Numo
Page 90 and 91: B.2 Query Structure Overview Numony
Page 92 and 93: Table 37: System Interface Informat
Page 94 and 95: B.6 Numonyx-Specific Extended Query
Page 96 and 97: Table 43: Partition Region 1 Inform
Page 98 and 99: Table 45: Partition and Erase-Block
Page 100 and 101: Table 47: 48F Type Stacked Componen
Page 102: Table 51: Parameter / Mux Configura
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Numonyxâ„¢ Wireless Flash Memory (W30)

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