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Figure 26: Interleaving a 2-Cycle Write Sequence with an Array Read<br />
Address [A]<br />
WE# [W]<br />
OE# [G]<br />
Data [Q]<br />
Numonyx <strong>Wireless</strong> <strong>Flash</strong> <strong>Memory</strong> (<strong>W30</strong>) (<strong>W30</strong>)<br />
Partition B Partition A Partition B Partition A<br />
FFh 20h Array Data D0h<br />
Read Array Erase Setup Bus Read Erase Conf irm<br />
By contrast, a write bus cycle must not interrupt a 2-cycle write sequence. Such an<br />
interruption causes a command sequence error to appear in the status register.<br />
Figure 27 illustrates a command sequence error.<br />
Figure 27: Improper Command Sequencing<br />
Address [A]<br />
WE# [W]<br />
OE# [G]<br />
Data [D/Q]<br />
Partition X Partition Y Partition X Partition X<br />
20h FFh D0h SR Data<br />
Datasheet November 2007<br />
54 Order Number: 290702-13
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