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Numonyx <strong>Wireless</strong> <strong>Flash</strong> <strong>Memory</strong> (<strong>W30</strong>)<br />
Figure 37, “Examples of VPP Power Supply Configurations” on page 78 shows examples<br />
of flash device power supply usage in various configurations.<br />
The 12-V V PP mode enhances programming performance during the short time period<br />
typically found in manufacturing processes. However, this mode is not intended for<br />
extended use.12 V can be applied to V PP during program and erase operations as<br />
specified in Section 5.2, “Operating Conditions” on page 24. VPP can be connected to<br />
12 V for a total of t PPH hours maximum. Stressing the flash device beyond these limits<br />
might cause permanent damage.<br />
11.3 Enhanced Factory Program (EFP)<br />
EFP substantially improves flash device programming performance through a number<br />
of enhancements to the conventional 12-Volt word program algorithm. The more<br />
efficient WSM algorithm in EFP eliminates the traditional overhead delays of the<br />
conventional word program mode in both the host programming system and the flash<br />
device. Changes to the conventional word programming flowchart and internal WSM<br />
routine were developed because of today's beat-rate-sensitive manufacturing<br />
environments; a balance between programming speed and cycling performance was<br />
attained.<br />
The host programmer writes data to the flash device and checks the Status Register to<br />
determine when the data has completed programming. This modification cuts write bus<br />
cycles approximately in half.<br />
• Following each internal program pulse, the WSM increments the flash device<br />
address to the next physical location.<br />
• Programming equipment can then sequentially stream program data throughout an<br />
entire block without having to setup and present each new address.<br />
In combination, these enhancements reduce much of the host programmer overhead,<br />
enabling more of a data streaming approach to flash device programming.<br />
EFP further speeds up programming by performing internal code verification. With this<br />
feature, PROM programmers can rely on the flash device to verify that it has been<br />
programmed properly. From the flash device side, EFP streamlines internal overhead by<br />
eliminating the delays previously associated with switching voltages between<br />
programming and verify levels at each memory-word location.<br />
EFP consists of four phases: setup, program, verify, and exit. Refer to Figure 29,<br />
“Enhanced Factory Program Flowchart” on page 64 for a detailed graphical<br />
representation of how to implement EFP.<br />
11.3.1 EFP Requirements and Considerations<br />
Table 24: EFP Requirements and Considerations<br />
EFP Requirements EFP Considerations<br />
Ambient temperature: TA = 25 °C ±5 °C Block cycling below 100 erase cycles 1<br />
VCC within specified operating range RWW not supported2 VPP within specified VPPH range EFP programs one block at a time<br />
Target block unlocked EFP cannot be suspended<br />
1. Recommended for optimum performance. Some degradation in performance might occur if this limit is exceeded, but the<br />
internal algorithm will continue to work properly.<br />
2. Code or data cannot be read from another partition during EFP.<br />
November 2007 Datasheet<br />
Order Number: 290702-13 61
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