Numonyxâ„¢ Wireless Flash Memory (W30)

11.3.2 Setup
Numonyx Wireless Flash Memory (W30) (W30)
After receiving the EFP Setup (30h) and EFP Confirm (D0h) command sequence, SR[7]
transitions from a 1 to a 0, indicating that the WSM is busy with EFP algorithm startup.
A delay before checking SR[7] is required to allow the WSM time to perform all of its
setups and checks (V PP level and block lock status). If an error is detected, status
register bits SR[4], SR[3], and/or SR[1] are set, and the EFP operation terminates.
Note: After the EFP Setup and Confirm command sequence, reads from the flash device
automatically output status register data. Do not issue the Read Status Register
command, because this command is interpreted as data to program at WA 0 .
11.3.3 Program
11.3.4 Verify
After setup completion, the host programming system must check SR[0] to determine
the data-stream ready status (SR[0]=0). Each subsequent write after this check is a
program-data write to the flash memory array. Each cell within the memory word to be
programmed to 0 receives one WSM pulse; additional pulses, if required, occur in the
verify phase.
SR[0]=1 indicates that the WSM is busy applying the program pulse.
The host programmer must poll the flash device status register for the program done
state after each data-stream write.
SR[0]=0 indicates that the appropriate cell(s) within the accessed memory location
have received their single WSM program pulse, and that the flash device is ready
for the next word.
Although the host can check full status for errors at any time, this check is necessary
only on a block basis, after EFP exit.
Addresses must remain within the target block. Supplying an address outside of the
target block immediately terminates the program phase; the WSM then enters the EFP
verify phase.
The address can either remain constant or increment. The flash device compares the
incoming address to the address stored from the setup phase (WA0 ).
• If the addresses match, the WSM programs the new data word at the next
sequential memory location.
• If the addresses differ, the WSM jumps to the new address location.
The program phase concludes when the host programming system writes to a different
block address. The data supplied must be FFFFh. Upon program phase completion, the
flash device enters the EFP verify phase.
A high percentage of the flash memory bits program on the first WSM pulse. However,
EFP internal verification identifies cells that do not completely program on their first
attempt, and applies additional pulses as required.
The verify phase is identical in flow to the program phase, except that instead of
programming incoming data, the WSM compares the verify-stream data to the data
that was previously programmed into the block.
• If the data compares correctly, the host programmer proceeds to the next word.
• If the data does not match, the host waits while the WSM applies one or more
additional pulses.
Datasheet November 2007
62 Order Number: 290702-13