Numonyxâ„¢ Wireless Flash Memory (W30)

20 ns + 4 ns ≤ 25 ns
This equation is satisfied, and data output is available and valid at every clock period. If
t DATA is long, hold for two cycles. During page-mode reads, the initial access time can be
determined using the formula:
t ADD-DELAY (ns) t DATA (ns) + t AVQV (ns)
Subsequent reads in page mode are defined by:
Note: WAIT shown asserted high (RCR[10]=1).
14.6 WAIT Delay (RCR[8])
t APA (ns) + t DATA (ns) (minimum time)
Figure 41: Data Output Configuration with WAIT Signal Delay
1 CLK
Data Hold
CLK [C]
WAIT (CR.8 = 1)
WAIT (CR.8 = 0)
DQ 15-0 [Q]
WAIT (CR.8 = 0)
WAIT (CR.8 = 1)
2 CLK
Data Hold DQ15-0 [Q]
t CHTL/H
The WAIT configuration bit (RCR[8]) controls WAIT signal delay behavior for all
synchronous read-array modes. This bit setting depends on the system and CPU
characteristics. The WAIT can be asserted either during, or one data cycle before, a
valid output.
In synchronous linear read array (no-wrap mode RCR[3]=1) of 4-word, 8-word, 16word,
or continuous-word burst mode, an output delay might occur when a burst
sequence crosses its first flash device-row boundary (16-word boundary).
• If the burst start address is 4-word boundary aligned, the delay does not occur.
• If the start address is misaligned to a 4-word boundary, the delay occurs once per
burst-mode read sequence. The WAIT signal informs the system of this delay.
14.7 Burst Sequence (RCR[7])
t CHQV
t CHQV
The burst sequence specifies the synchronous-burst mode data order (see Table 30,
“Sequence and Burst Length” on page 84). When operating in a linear burst mode,
either 4-word, 8-word, or 16-word burst length with the burst wrap bit (RCR[3]) set, or
in continuous burst mode, the flash device might incur an output delay when the burst
sequence crosses the first 16-word boundary. (See Figure 39, “Word Boundary” on
page 81 for word boundary description.)
Valid
Output
Note 1
Note 1
Note 1
Note 1
Valid
Output
Valid
Output
Valid
Output
Valid
Output