Accutorr Plus Service Manual - Mindray

Real Time Clock and NV RAM (RTC), U28
The RTC is a bus device that will keep track of seconds, minutes, hours, date of the
month, month, day of the week, and year with leap year compensation. The module
contains a 10 year lithium source and internal crystal. The independent Lithium battery
is a back up so that in case AC power is not on, the battery voltage will keep the time up
to date.
Also included in the device is 2K X 8 nonvolatile RAM. This ram is continuous addressed
above the RTC information.
NIBP Control, U13, U14, U15, U16
U15 is used to create an over pressure latch, that will monitor OVPR_DET*, for a hardware
over pressure situation. When this circuit is tripped, the pneumatic drivers will be
disengaged, and no NIBP functions will exist until a power-on reset occurs. The over
pressure signal may have inadvertent triggers. In order for OVPR_DET* to trigger the
latch, it must be active low for 66ms min, due to C11, R16, and R15.
U15, also is used for a pneumatic safety latch. In the case of a MC68302 clock failure, the
pneumatic drivers will be disengaged upon a power-on reset. If the clock is running, then
the software will toggle EN_PNEU*, to enable the drivers and NIBP functions will work.
Upon power on reset, the following sequence must be met in order for the over pressure
and pneumatic safety latches to be initialized properly: U15-1 must go to a logic hi 76ns
min before RST* rises to a logic hi, and RST* must go to a logic hi 76ns min before
EN_PNEU* toggles logic low to a logic hi. The pneumatic drivers are made up of U14,
U13, and U16. These gates are used for the turn on of the pump, dump valve, linear
valve, and other controls. As discussed above, they will only work given the proper
initialization or no fault condition.
The serial clock to the NIBP A/D, TLC2543, is controlled via U13. SPCLK comes from
the SCP of the MC68302 and is gated by SPCLKEN* to form SER_CLK. SPCLK cannot
be higher than 4.1MHz. AD_CS* is the enable to the chip select input of the device.
EOC is an output signal of the A/D, and specifies an end of conversion. It goes hi to low
and remains low until a conversion is completed and data is ready for transfer. AD_CS*
must be active low for 1.425us before SER_CLK starts toggling. EOC will go low 2.2us
max from last SER_CLK.
Recorder interface
The recorder interface is a buffered 8 bit parallel data bus with handshaking and reset
capability through connector J5. The buffering provides pass through filtering and ESD
suppression is provided by U35. WR_RECD* is driven by the LED/CPU board and used
by the recorder to latch the data bus. This interface is handled by the DMA capability of
the MC68302. The recorder drives two signals, DREQ*, and HOME*. DREQ* specifies
to the MC68302 to send the next byte of data. HOME* will specify when the recorder
has reached its starting point to begin a new line.
2-14 Revised 12/20/00
Accutorr Plus Service Manual
Chapter 2 - Theory of Operation