A GEM Detector System for an Upgrade of the CMS Muon Endcaps

ates and the need for compatibility with the GBT mean that a new ASIC will be required for the future. In the
following we provide an overview of the VFAT2 chip before leading on to the design requirements for a new
front-end chip (VFAT3/GdSP).
VFAT2 The VFAT2 chip (Fig. 61) is a trigger and tracking front-end ASIC, initially designed for the readout
of silicon and gas sensors of the TOTEM experiment. It has two main functions; the first (Trigger) is to provide
programmable “fast OR” information based on the region of the sensor hit. This can be used for the creation of a
trigger. The second function (Tracking) is for providing precise spatial hit information for a given triggered event.
The possibility of these two functions plus internal input protection for use with GEMs make VFAT2 the ideal
(existing) candidate for the readout of the current GEM prototypes.
Figure 61: VFAT2, A 128 channel front-end ASIC with trigger and tracking capabilities. This ASIC is currently
used for the prototype systems.
Fig. 62 shows the block diagram for VFAT2.
128 channels
Analog input
Calibration
Preamp and shaper
DACs
I2C
Receiver and
Registers
SDA SCL
Analog Digital
Comparator
Digital
I/P
Sector
Logic
Sync &
Monostable
SRAM1
Hamming
Enc. & Dec
Control Logic
SRAM2
T1
( LV1A, ReSync, CalPulse, BC0 )
Figure 62: The VFAT2 architecture, shown for 1 channel.
8 Sector O/Ps
(LVDS)
Data
Formatter
DataOut
(LVDS)
Contains:
Column data
BC
EC
ChipID
CRC
checksum
It has 128 analog input channels each of which are equipped with a very low noise pre-amplifier and shaping
stage plus comparator. A calibration unit allows delivery of controlled test pulses to any channel for calibration
purposes. Signal discrimination on a programmable threshold provides binary “hit” information which passes
through a synchronisation unit and then stored within SRAMs until a trigger is received. The storage capacity
enables trigger latencies of up to 6.4 µs and the simultaneous storage of data for up to 128 triggered events. Dead
time free operation with up to 100kHz Poisson distributed trigger rates is ensured. Time and event tags are added
to the triggered data which are then formatted and read from the chip in the form of digitized data packets at 40
Mbps. The programmability is achieved through and I 2 C interface whilst the fast ports are LVDS.
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