A GEM Detector System for an Upgrade of the CMS Muon Endcaps

6.4.2 Segmentation
The GEM chamber is sub divided into columns and eta partitions as shown in Fig. 68.
GEM chamber segmentation
FE ASIC C
Segments
(ie Segment A3) 3)
GBTs
A B C
Columns
1
2
3
.
.
.
.
.
Eta partitions
Figure 68: The GEM segmentation into columns and eta partitions.
The segmentation of the GEM chamber has many implications, the main ones are noise, rate capability, power and
cost. One can summarise the general effects as in Table 5
Table 5: Summary table
Increasing Eta Partitions Increasing columns
Area cover by one chip ց ց
Strip area and capacitance ց ց
Noise ց ց
Strip pitch - ց
Rate capability ր ? ց
Power ր ր
Cooling needs ր ր
Cost ր ր
The optimal balance between all of these factors is a delicate study which is not yet completed. For GE1/1 we
have so far considered columns-eta partitions of 3-4, 3-8 and 3-16 creating 12, 24 and 48 sectors respectively. A
fourth possibility of 3-10 is also under consideration as this provides the optimum usage of bandwidth of the GBT.
This is because (at the maximum GBT E-Link frequency of 320Mbps) the GBT can communicate with up to 10
front-end chips. Hence a 3-10 configuration requires one GBT and one optical fibre per column with 10 front-end
ASICs per column. Initial studies of rate capability show that operation with a 3-10 configuration with a hit rate of
< 10kHz/cm 2 is possible.
6.4.3 Electronics power consumption for a 3·10 chamber.
The chamber is designed as an individual element in order to allow for flexibility in terms of number of chambers
and number of layers in a system. Here the power and cost is calculated for a single 3-10 single chamber. A double
layer super-chamber is also double the power of a single chamber. Table 6 shows the estimated power consumption
of the principle electronic components used. These numbers can be considered an upper limit.
6.5 Project planning
Time planning The design of the front-end ASIC can be broken down into 4 phases as detailed in Table 7. Phase
1 covers the specification phase. This phase began in 2011 and is expected to be complete by the second quarter of
2012. Phase 2 is the design of the individual electronic modules while phase 3 is the integration of these modules
into a complete chip. Following fabrication phase 4 covers the prototype testing phase. Table 7 gives the estimated
man months for the different elements and phases totaling an estimated 8 man years for the project. These numbers
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