A GEM Detector System for an Upgrade of the CMS Muon Endcaps

VFAT3 The VFAT architecture is the baseline front-end ASIC architecture for the CMS GEM system. However,
the requirements for the system, whilst very similar to those of TOTEM, differ in some very important ways that
make the design and optimization of a new front-end ASIC a necessity. The main differences are listed below:
1. Operation at high particle rate using large GEM detectors
2. Precise and clean trigger information at very high rate (≈2.3MHz/chip)
3. Large detector capacitance 20 - 60pF
4. Relatively long signal charge collection ≈80ns
5. Interface required : slvds elinks to GBT (as opposed to I 2 C and LVDS)
6. Integrated calibration, bias and monitoring functions,
Preamp Shaper
VFAT3
128 channels
CBM Unit
(Calibration, Bias &
Monitoring)
Comparator
TOT,
Sync.
&
Trigger
Logic
SRAM
Configuration Registers
Figure 63: VFAT3 architecture.
Data Controller
&
Control Logic
The block diagram for VFAT3 is shown in Fig. 63. Similarly to VFAT2 it will have 128 channels of preamplifier,
shaper and comparator. The shaping time and gain will be programmable in order to optimize the signal charge
collection from the GEM detector whilst maintaining excellent timing resolution (≈4.5ns rms for VFAT2). A
longer shaping time will result in improved signal to noise ratio when used with GEM detectors due to reduced
ballistic deficit. This in turn will reduce sensitivity to baseline pedestal jumps which can otherwise contribute to the
noise. However increased shaping times come at the cost of degrading time-resolution due to increased time-walk.
To avoid this degradation of time resolution we are studying the implementation of digital “Time Over Threshold”
(TOT) techniques to compensate for time walk and restore the original time resolution. The binary “hit” data and
associated time tag are then buffered in SRAM memory before being readout in data packets at 320Mbps via the
e-port. Slow control functions also communicate via the e-link to the outside world. The CMB unit provides
internal circuitry for the slow control functions of calibration, biasing and monitoring. This avoids the need for an
additional slow control ASIC.
GdSP The GdSP architecture is very similar to that previously described for VFAT3 with the same resulting
data packet content. However instead of using a comparator plus TOT, the GdSP incorporates an ADC to digitise
samples from the preamplifier and shaper. Until recently it would have been unthinkable to have an ADC per
channel due to the ADC power demands. However, very rapid advance of ADC design techniques in recent years
now make it possible to design ADCs with an order of magnitude less power than 2-3 years ago. It is hence now
possible to have an ADC per channel on a 128 channel chip with ADC power consumption < 4mW / channel.
Once samples have been digitized by the ADC, digital signal processing and filtering can be employed to reduce
common mode effects and background artifacts. This in turn enables very clean signal discrimination for the
creation of a trigger.
The block diagram for the GdSP chip is shown in Fig. 64. Note that VFAT3 and GdSP share most of the important
building blocks, differing only with respect to comparator + TOT verses ADC+DSP.
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E-Port