A GEM Detector System for an Upgrade of the CMS Muon Endcaps

FE ASIC Readout systems
Define electronics system for TP,
Formation of design teams.
ASIC design to start
Submission of FE AISC (VFAT3/
GdSP)
FE ASIC design
team
Approx. 8 man
years of design
time needed.
2012
2014
2011
From
~ 2014
2015
Present : VFAT2 , Turbo hardware and Labview
DAQ software
Medium
term : VFAT2 + SRS
uCTA (off detector
electronics development)
Future : VFAT3/GDSP + GBT + uCTA off
detector electronics.
System running with all final components
Figure 69: Time line for the front-end ASIC development and readout systems.
The Present readout system is based on the VFAT2 chip working together with the Turbo readout board. This
system has been in use throughout 2011 and expected to continue into 2012. The SRS [15] readout system has
been commonly used for small prototype systems for GEM detector development. An SRS system compatible
with VFAT2 is foreseen for the medium term to enable collaborators easy access to electronics for GEM detector
development. In addition the development of the final off-detector system will take place during this medium term
period occupying 2012 and 2013. The time scale is such that the FE ASIC, GBT chipset and off-detector uCTA
readout system should be ready for the assembly of the final system by 2015. The production of components
should be started from 2015.
A one year production period is reasonable while a two year assembly period should be anticipated.
6.6 Cost:
6.6.1 On-detector costs
FE ASIC silicon costs: The technology currently foreseen for the fabrication of the front-end ASIC is a CMOS
130nm process. The reason for this choice was largely related to the existence of device libraries and many useful
building blocks and cost. The cost of fabricating a design in 130nm is approximately half that of fabricating in a
more advanced 65nm process. ASIC designs can be submitted to the foundry either as an (Multi Project Wafer)
MPW run or as a dedicated engineering run. MPW runs shared the silicon mask cost with other projects and hence
have reduced cost. This is ideal for prototyping small circuits and modules. The engineering run is for production.
In an engineering run one project is submitted yielding many more chips. Table 8 summarises the current cost of
an MPW run and an engineering run in this process.
Table 8: Silicon fabrication cost of an MPW run and an engineering run in this process.
Run Type Cost Number of chips Use
MPW Run $ 3.25k/mm 2 , (≈50k) 40 Prototyping
Engineering Run $ 400 + $3k/wafer 6480 Production
(min quantity = 24 wafers) therefore $522k (assuming a slightly larger
area compared to VFAT2)
In order to make an estimate of the price per front-end chip from an engineering run we have to make a few
assumptions on number of chips per wafer, yield, dicing and packaging cost. Hence assuming 300 chips per
wafer, 90% yield, packaging cost at $ 20k + $ 2/piece the total price per chip is $ 78 with a minimum investment
of $ 506.4k .
65