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A GEM Detector System for an Upgrade of the CMS Muon Endcaps

A GEM Detector System for an Upgrade of the CMS Muon Endcaps

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algorithm, <strong>the</strong> GemTBs input data b<strong>an</strong>dwidth <strong>an</strong>d <strong>the</strong> number <strong>an</strong>d size <strong>of</strong> FPGAs used <strong>for</strong> executing <strong>the</strong> trigger<br />

algorithm. If <strong>the</strong> <strong>GEM</strong> chambers are doubled (to <strong>for</strong>m superchambers) in <strong>the</strong> first <strong>an</strong>d second station, <strong>the</strong>n <strong>the</strong><br />

trigger algorithm c<strong>an</strong> use a delta phi between <strong>the</strong> hits in <strong>the</strong> doubled layers <strong>of</strong> <strong>the</strong> same station to improve <strong>the</strong> muon<br />

momentum measurement. For that, <strong>the</strong> full gr<strong>an</strong>ularity <strong>of</strong> <strong>the</strong> <strong>GEM</strong>s would be needed. This c<strong>an</strong>not be per<strong>for</strong>med<br />

by <strong>the</strong> current RPC TBs, as in option A, because it would not be possible to tr<strong>an</strong>smit full gr<strong>an</strong>ularity <strong>GEM</strong> data to<br />

<strong>the</strong> current TBs. There<strong>for</strong>e option B (or C) would be <strong>the</strong> preferred choice in <strong>the</strong> case <strong>of</strong> superchambers.<br />

The maximum latency <strong>of</strong> <strong>the</strong> high-η muon c<strong>an</strong>didates at <strong>the</strong> input <strong>of</strong> <strong>the</strong> Trigger Crate GBSort chip c<strong>an</strong>not exceed<br />

≈70 BX.<br />

Option C: Updating <strong>the</strong> entire RPC PAC Trigger <strong>System</strong> Recently, discussions within <strong>the</strong> <strong>CMS</strong> Collaboration<br />

have started about possibly updating <strong>the</strong> entire trigger electronics around <strong>the</strong> year 2020. While a discussion on <strong>the</strong><br />

new PAC Trigger system is premature <strong>an</strong>d out <strong>of</strong> <strong>the</strong> scope <strong>of</strong> this document, <strong>the</strong> <strong>GEM</strong> <strong>of</strong>f-detector Electronics<br />

system must also provide <strong>for</strong> <strong>the</strong> possibility <strong>of</strong> a new RPC link system also built using <strong>the</strong> GBT-GLIB concept<br />

with <strong>the</strong> trigger algorithm per<strong>for</strong>med in new electronics hosted in aµTCA crate. This system would hence be very<br />

similar to <strong>the</strong> one <strong>for</strong> <strong>the</strong> high-η <strong>GEM</strong>s in <strong>the</strong> option B, except that <strong>the</strong> muons c<strong>an</strong>didates from <strong>the</strong> entire system<br />

would be ghost busted <strong>an</strong>d sorted in a new Final Sorter µTCA crate.<br />

6.4 <strong>System</strong> considerations<br />

6.4.1 General system view<br />

DC/DC converters<br />

<strong>GEM</strong><br />

Front-ends<br />

VFAT/GdSP<br />

GBT<br />

Optical link @ 3.2Gbps<br />

Counting room<br />

~10V<br />

GLIB<br />

Ser/Des<br />

LV<br />

HV<br />

Interface <strong>an</strong>d<br />

driver board<br />

Power Supplies<br />

Figure 67: Block diagram <strong>for</strong> <strong>the</strong> electronics system (control <strong>an</strong>d readout) as <strong>for</strong>eseen <strong>for</strong> <strong>the</strong> <strong>CMS</strong> <strong>for</strong>ward high-η<br />

region.<br />

Custom<br />

FPGAs<br />

Firmware<br />

&<br />

S<strong>of</strong>tware<br />

PAC Trigger<br />

Fig. 67 shows <strong>the</strong> block diagram <strong>for</strong> <strong>the</strong> system. A brief summary <strong>of</strong> <strong>the</strong> system is as follows:<br />

1. One <strong>GEM</strong> chamber is segmented into different eta regions <strong>an</strong>d columns creating <strong>GEM</strong> segments.<br />

2. Each <strong>GEM</strong> segment is subdivided into 128 strips or ch<strong>an</strong>nels.<br />

3. One front-end ASIC (VFAT3/GdSP) is used per <strong>GEM</strong> segment to readout <strong>the</strong> charge deposited in each <strong>GEM</strong><br />

ch<strong>an</strong>nel.<br />

4. Power is delivered to <strong>the</strong> <strong>GEM</strong> chamber by electrical cables. Local DC/DC regulators condition <strong>the</strong> voltage<br />

to <strong>the</strong> levels required by <strong>the</strong> on-detector electronics.<br />

5. E-links (electrical SLVDS pairs) connect <strong>the</strong> front-end ASICs to <strong>the</strong> GBT chipset.<br />

6. The GBT chipset multiplexes to <strong>an</strong>d from <strong>the</strong> front-end ASIC <strong>an</strong>d receives/tr<strong>an</strong>smits data between <strong>the</strong> inner<br />

<strong>an</strong>d outer detector regions via optical fibres.<br />

7. The <strong>of</strong>f-detector electronics within <strong>the</strong> counting room has <strong>an</strong> interface <strong>an</strong>d driver unit providing <strong>the</strong> interface<br />

to <strong>the</strong> <strong>CMS</strong> trigger, DAQ, DCS <strong>an</strong>d TTC systems as well as allowing integration to <strong>the</strong> existing PAC trigger.<br />

This basic system is highly flexible to different <strong>GEM</strong> geometries <strong>an</strong>d segmentation configurations. For <strong>the</strong> GE1/1<br />

region <strong>of</strong> <strong>CMS</strong>, each <strong>GEM</strong> chamber will cover <strong>an</strong> arc <strong>of</strong> approximately 10 degrees, <strong>the</strong>re<strong>for</strong>e <strong>the</strong>re will be 36<br />

chambers in a ring. In <strong>the</strong> case <strong>of</strong> a double layer using super chambers <strong>the</strong>re will be 72 <strong>GEM</strong> chambers per ring.<br />

62<br />

Trigger<br />

DAQ<br />

DCS<br />

TTC<br />

Trigger

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