Intel Server Board S1200BT - PROconsult Data A/S

Design and Environmental Specifications
Intel® Server Board S1200BT TPS
Table 53. Turn On/Off Timing
Item Description Minimum Maximum Units
T sb _on_delay Delay from AC being applied to 5 VSB being
Msec
N/A 1500
within regulation.
T ac _on_delay
T vout _holdup
T pwok _holdup
T pson _on_delay
T pson _pwok
T pwok _on
T pwok _off
T pwok _low
T sb _vout
T 5VSB _holdup
Delay from AC being applied to all output voltages
being within regulation.
Duration for which all output voltages stay within
regulation after loss of AC. Measured at 80% of
maximum load.
Delay from loss of AC to de-assertion of PWOK.
Measured at 80% of maximum load.
Delay from PSON# active to output voltages
within regulation limits.
Delay from PSON# deactive to PWOK being deasserted.
Delay from output voltages within regulation limits
to PWOK asserted at turn on.
Delay from PWOK de-asserted to output voltages
(3.3 V, 5 V, 12 V, -12 V) dropping out of regulation
limits.
Duration of PWOK being in the de-asserted state
during an off/on cycle using AC or the PSON
signal.
Delay from 5 VSB being in regulation to O/Ps
being in regulation at AC turn on.
Duration for which the 5 VSB output voltage stays
within regulation after loss of AC.
N/A 2500
21 N/A
20 N/A
5 400
N/A 50
100 500
1 N/A
100 N/A
50 1000
70 N/A
Msec
Msec
Msec
Msec
Msec
Msec
Msec
Msec
Msec
Msec
Figure 50. Turn On/Off Timing (Power Supply Signals)
116
Intel order number G13326-003
Revision 1.0