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TMT<br />
<strong>Memory</strong> Devices Technology<br />
8 October 2010<br />
abc<br />
Stronger balance sheets repaired through<br />
recapitalisation and lower losses/better<br />
profitability, and<br />
Intensifying technology competition (more<br />
advanced processes, multi-bit) to drive better<br />
margins, market positioning.<br />
We expect industry-wide migration to more<br />
advanced processes to lower cost/bit, raising<br />
margins:<br />
Samsung started mass producing 27nm-process<br />
based NAND in April 2010 (development<br />
completed in October 2009) and recently<br />
launched 27nm 32Gb MLC NAND.<br />
Toshiba started mass production of 24nmbased<br />
64Gb MLC NAND in 3Q10, expanding<br />
to include 24nm-based 32Gb NAND and TLC<br />
at a later point. This appears ahead of its<br />
original schedule to achieve 24nm migration<br />
(X2, X3) production by 4Q10 and mass<br />
production in 2011. Like Samsung and Hynix,<br />
Toshiba’s 24nm process products have<br />
Toggle DDR to enhance data transfer speeds.<br />
Intel and Micron (IMFT – Intel Micron Flash<br />
Technologies)’s 25nm-process based 64GB<br />
NAND mass production started in 2Q10.<br />
Hynix is admittedly late to 3xnm, but believes<br />
it has caught up with leading vendors with its<br />
2xnm migration. Hynix plans mass<br />
production in 3Q10 for its 26nm process<br />
based 64GB NAND. We believe Hynix has<br />
customer samples out for this product.<br />
current processes. By 2014-15 EUV lithography is<br />
a likely requirement for the migration to processes<br />
below 1x nm.<br />
Wafer capacity increases<br />
Wafer capacity was relatively stable in the past<br />
two years, helped by removal of uneconomic<br />
200mm fab capacity. This year, we estimate wafer<br />
capacity to increase c14% y-o-y as process<br />
migration accelerates and additional fab capacity<br />
starts to get built out. Next year, we forecast c20%<br />
increase in wafer capacity, led by Toshiba and<br />
possibly Samsung.<br />
SanDisk/Toshiba<br />
SanDisk is focussed on upgrading processes and<br />
implementing X3 in Fab 3 and Fab 4.<br />
Fab 4 expansion. This year, Toshiba has ramped<br />
previously unused space in Fab 4, which should<br />
reach full capacity by mid-2011, i.e. by the<br />
completion of Phase 1 of Fab 5. The original<br />
design wafer capacity of Fab 4 is 210kwpm, but<br />
we expect Toshiba to produce more given<br />
throughput improvements it has made.<br />
Fab 5 finally gets the go ahead. In mid-July<br />
2010 Toshiba started construction of Fab 5 at<br />
Yokkaichi. Notably it is capable of supporting<br />
EUV and 3D flash. Fab 5 will be constructed in<br />
two phases; SanDisk expects the fab to take<br />
several years to ramp to full capacity. Phase 1 will<br />
be producing 24nm process based NAND, whilst<br />
Phase 2, for which timing has not been decided,<br />
will produce 1xnm generation NAND.<br />
One key question that remains unanswered is<br />
capex from 2012e onwards, as vendors ponder the<br />
comparative returns on migration to 1xnm.<br />
Toshiba and Samsung remains undecided over<br />
how to tackle this issue, though both firms are<br />
evaluating EUV. SanDisk expects to be on 1xnm<br />
(X2 and X3) by end 2012/early 2013. But at that<br />
level, the technology is more ‘challenging’ than<br />
50