PIC16F84A 18-pin Enhanced Flash/EEPROM 8-Bit MCU Data Sheet

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PIC16F84AFIGURE 3-2:BLOCK DIAGRAM OF PIN RA4DatabusWRPORTD QCK QData LatchNRA4 pinWRTRISD QCK QTRIS LatchVSSSchmittTriggerinputbufferRD TRISQDRD PORTENTMR0 clock inputNote: I/O pin has protection diodes to VSS only.TABLE 3-1 PORTA FUNCTIONSName Bit0 Buffer Type FunctionRA0 bit0 TTL Input/outputRA1 bit1 TTL Input/outputRA2 bit2 TTL Input/outputRA3 bit3 TTL Input/outputRA4/T0CKI bit4 ST Input/output or external clock input for TMR0.Output is open drain type.Legend: TTL = TTL input, ST = Schmitt Trigger inputTABLE 3-2SUMMARY OF REGISTERS ASSOCIATED WITH PORTAAddress Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0Value onPower-onResetValue on allother resets05h PORTA — — — RA4/T0CKI RA3 RA2 RA1 RA0 ---x xxxx ---u uuuu85h TRISA — — — TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 ---1 1111 ---1 1111Legend:x = unknown, u = unchanged, - = unimplemented read as '0'. Shaded cells are unimplemented, read as '0'DS35007A-page 14 Preliminary © 1998 Microchip Technology Inc.
PIC16F84A3.2 PORTB and TRISB RegistersPORTB is an 8-bit wide bi-directional port. The correspondingdata direction register is TRISB. Setting aTRISB bit (=1) will make the corresponding PORTB pinan input, i.e., put the corresponding output driver in ahi-impedance mode. Clearing a TRISB bit (=0) willmake the corresponding PORTB pin an output, i.e., putthe contents of the output latch on the selected pin.EXAMPLE 3-1: INITIALIZING PORTBBCF STATUS, RP0 ;CLRF PORTB ; Initialize PORTB by; clearing output; data latchesBSF STATUS, RP0 ; Select Bank 1MOVLW 0xCF; Value used to; initialize data; directionMOVWF TRISB ; Set RB as inputs; RB as outputs; RB as inputsEach of the PORTB pins has a weak internal pull-up. Asingle control bit can turn on all the pull-ups. This is performedby clearing bit RBPU (OPTION). The weakpull-up is automatically turned off when the port pin isconfigured as an output. The pull-ups are disabled on aPower-on Reset.FIGURE 3-3:RBPU (1)Data busWR PortBLOCK DIAGRAM OF PINSRB7:RB4Data LatchDCKQFour of PORTB’s pins, RB7:RB4, have an interrupt onchange feature. Only pins configured as inputs cancause this interrupt to occur (i.e. any RB7:RB4 pin configuredas an output is excluded from the interrupt onchange comparison). The input pins (of RB7:RB4) arecompared with the old value latched on the last read ofPORTB. The “mismatch” outputs of RB7:RB4 areOR’ed together to generate the RB Port Change Interruptwith flag bit RBIF (INTCON).This interrupt can wake the device from SLEEP. Theuser, in the interrupt service routine, can clear the interruptin the following manner:a) Any read or write of PORTB. This will end themismatch condition.b) Clear flag bit RBIF.A mismatch condition will continue to set flag bit RBIF.Reading PORTB will end the mismatch condition, andallow flag bit RBIF to be cleared.The interrupt on change feature is recommended forwake-up on key depression operation and operationswhere PORTB is only used for the interrupt on changefeature. Polling of PORTB is not recommended whileusing the interrupt on change feature.FIGURE 3-4:BLOCK DIAGRAM OF PINSRB3:RB0RBPU (1) weakPpull-upData LatchData busD QVDDI/OWR Portpin (2)weakCKPpull-upTRIS LatchD QTTLI/Opin (2) WR TRISInputCKBufferVDDWR TRISTRIS LatchD QCKTTLInputBufferRD TRISRD PortQDENSet RBIFRD TRISRD PortFrom otherRB7:RB4 pinsLatchQ DENQ DRB0/INTNoteSchmitt TriggerBuffer1: TRISB = '1' enables weak pull-up(if RBPU = '0' in the OPTION_REG register).2: I/O pins have diode protection to VDD and VSS.RD PortENRD PortNote1: TRISB = '1' enables weak pull-up(if RBPU = '0' in the OPTION_REG register).2: I/O pins have diode protection to VDD and VSS.© 1998 Microchip Technology Inc. Preliminary DS35007A-page 15
Page 1 and 2: MPIC16F84A18-pin Enhanced Flash/EEP
Page 3 and 4: PIC16F84A1.0 DEVICE OVERVIEWThis do
Page 5 and 6: PIC16F84A2.0 MEMORY ORGANIZATIONThe
Page 7 and 8: PIC16F84A2.2.2 SPECIAL FUNCTION REG
Page 9 and 10: PIC16F84A2.2.2.2 OPTION_REG REGISTE
Page 11 and 12: PIC16F84A2.3 PCL and PCLATHThe prog
Page 13: PIC16F84A3.0 I/O PORTSSome pins for
Page 17 and 18: PIC16F84A4.0 TIMER0 MODULEThe Timer
Page 19 and 20: PIC16F84A5.0 DATA EEPROM MEMORYThe
Page 21 and 22: PIC16F84A6.0 SPECIAL FEATURES OF TH
Page 23 and 24: PIC16F84A6.2.3 RC OSCILLATORFor tim
Page 25 and 26: PIC16F84A6.4 Power-on Reset (POR)A
Page 27 and 28: PIC16F84AFIGURE 6-9:TIME-OUT SEQUEN
Page 29 and 30: PIC16F84A6.8.1 INT INTERRUPTExterna
Page 31 and 32: PIC16F84A6.11 Power-down Mode (SLEE
Page 33 and 34: PIC16F84A7.0 INSTRUCTION SET SUMMAR
Page 35 and 36: PIC16F84A8.0 DEVELOPMENT SUPPORT8.1
Page 37 and 38: PIC16F84A8.10 MPLAB Integrated Deve
Page 39 and 40: © 1998 Microchip Technology Inc. P
Page 41 and 42: PIC16F84A9.0 ELECTRICAL CHARACTERIS
Page 43 and 44: PIC16F84A9.1 DC CHARACTERISTICS: PI
Page 45 and 46: PIC16F84A9.3 DC CHARACTERISTICS: PI
Page 47 and 48: PIC16F84A9.5 AC (Timing) Characteri
Page 49 and 50: PIC16F84A9.5.3 TIMING DIAGRAMS AND
Page 51 and 52: PIC16F84AFIGURE 9-5:RESET, WATCHDOG
Page 53 and 54: PIC16F84A10.0 DC & AC CHARACTERISTI
Page 55 and 56: PIC16F84A11.0 PACKAGING INFORMATION
Page 57 and 58: PIC16F84A11.3 K04-051 18-Lead Plast
Page 59 and 60: PIC16F84AAPPENDIX A: REVISION HISTO
Page 61 and 62: PIC16F84ANOTES:© 1998 Microchip Te
Page 63 and 64: PIC16F84AINDEXAAbsolute Maximum Rat
Page 65 and 66:
PIC16F84AON-LINE SUPPORTMicrochip p
Page 67 and 68:
PIC16F84APIC16F84A PRODUCT IDENTIFI
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PIC16F84A 18-pin Enhanced Flash/EEPROM 8-Bit MCU Data Sheet

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