<strong>PIC16F84A</strong>APPENDIX C: MIGRATION FROMBASELINE TOMIDRANGE DEVICESThis section discusses how to migrate from a baselinedevice (i.e., PIC16C5X) to a midrange device (i.e.,PIC16CXXX).The following is the list of feature improvements overthe PIC16C5X microcontroller family:1. Instruction word length is increased to 14 bits.This allows larger page sizes both in programmemory (2K now as opposed to 512 before) andthe register file (128 bytes now versus 32 bytesbefore).2. A PC latch register (PCLATH) is added to handleprogram memory paging. PA2, PA1 and PA0 bitsare removed from the status register and placedin the option register.3. <strong>Data</strong> memory paging is redefined slightly. TheSTATUS register is modified.4. Four new instructions have been added:RETURN, RETFIE, ADDLW, and SUBLW. Twoinstructions, TRIS and OPTION, are beingphased out although they are kept forcompatibility with PIC16C5X.5. OPTION and TRIS registers are madeaddressable.6. Interrupt capability is added. Interrupt vector isat 0004h.7. Stack size is increased to 8 deep.8. Reset vector is changed to 0000h.9. Reset of all registers is revisited. Five differentreset (and wake-up) types are recognized.Registers are reset differently.10. Wake up from SLEEP through interrupt isadded.11. Two separate timers, the Oscillator Start-upTimer (OST) and Power-up Timer (PWRT), areincluded for more reliable power-up. Thesetimers are invoked selectively to avoidunnecessary delays on power-up and wake-up.12. PORTB has weak pull-ups and interrupt onchange features.13. T0CKI <strong>pin</strong> is also a port <strong>pin</strong> (RA4/T0CKI).14. FSR is a full 8-bit register.15. "In system programming" is made possible. Theuser can program PIC16CXX devices using onlyfive <strong>pin</strong>s: VDD, VSS, VPP, RB6 (clock) and RB7(data in/out).To convert code written for PIC16C5X to <strong>PIC16F84A</strong>,the user should take the following steps:1. Remove any program memory page selectoperations (PA2, PA1, PA0 bits) for CALL, GOTO.2. Revisit any computed jump operations (write toPC or add to PC, etc.) to make sure page bitsare set properly under the new scheme.3. Eliminate any data memory page switching.Redefine data variables for reallocation.4. Verify all writes to STATUS, OPTION, and FSRregisters since these have changed.5. Change reset vector to 0000h.DS35007A-page 62 Preliminary © 1998 Microchip Technology Inc.
<strong>PIC16F84A</strong>INDEXAAbsolute Maximum Ratings ............................................... 41AC (Timing) Characteristics ............................................... 47Architecture, Block Diagram ................................................ 3AssemblerMPASM Assembler .................................................... 37BBanking, <strong>Data</strong> Memory .................................................... 6, 8CCLKIN Pin ............................................................................ 4CLKOUT Pin ........................................................................ 4Code Protection ........................................................... 21, 32Configuration <strong>Bit</strong>s ............................................................... 21Conversion Considerations ................................................ 59D<strong>Data</strong> <strong>EEPROM</strong> Memory ..................................................... 19EEADR Register .................................................... 7, 24EECON1 Register ............................................ 7, 19, 24EECON2 Register ............................................ 7, 19, 24EEDATA Register .................................................. 7, 24Write Complete Enable (EEIE <strong>Bit</strong>) ....................... 10, 29Write Complete Flag (EEIF <strong>Bit</strong>) ............................ 19, 29<strong>Data</strong> <strong>EEPROM</strong> Write Complete ......................................... 29<strong>Data</strong> Memory ....................................................................... 6Bank Select (RP0 <strong>Bit</strong>) .............................................. 6, 8Banking ........................................................................ 6DC & AC Characteristics Graphs/Tables ........................... 53DC Characteristics ........................................... 43, 44, 45, 46Development Support ........................................................ 35Development Tools ............................................................ 35EEECON1 Register .............................................................. 19EEIF <strong>Bit</strong> ................................................................ 19, 29RD <strong>Bit</strong> ......................................................................... 19WR <strong>Bit</strong> ........................................................................ 19WREN <strong>Bit</strong> ................................................................... 19WRERR <strong>Bit</strong> ................................................................ 19Electrical Characteristics .................................................... 41Endurance ............................................................................ 1Errata ................................................................................... 2External Power-on Reset Circuit ........................................ 25FFirmware Instructions ......................................................... 33ftp site ................................................................................ 65Fuzzy Logic Dev. System (fuzzyTECH®-MP) ................... 37II/O Ports ............................................................................. 13ICEPIC Low-Cost PIC16CXXX In-Circuit Emulator ........... 35ID Locations ................................................................. 21, 32In-Circuit Serial Programming (ICSP) .......................... 21, 32Indirect Addressing ............................................................ 11FSR Register ............................................... 6, 7, 11, 24INDF Register ........................................................ 7, 24Instruction Format .............................................................. 33Instruction Set .................................................................... 33Summary Table .......................................................... 34INT Interrupt (RB0/INT) ...................................................... 29INTCON Register ........................................ 7, 10, <strong>18</strong>, 24, 28EEIE <strong>Bit</strong> ............................................................... 10, 29GIE <strong>Bit</strong> ........................................................... 10, 28, 29INTE <strong>Bit</strong> ............................................................... 10, 29INTF <strong>Bit</strong> ............................................................... 10, 29RBIE <strong>Bit</strong> ............................................................... 10, 29RBIF <strong>Bit</strong> ......................................................... 10, 15, 29T0IE <strong>Bit</strong> ................................................................ 10, 29T0IF <strong>Bit</strong> .......................................................... 10, <strong>18</strong>, 29Interrupt Sources ......................................................... 21, 28Block Diagram ........................................................... 28<strong>Data</strong> <strong>EEPROM</strong> Write Complete ........................... 28, 31Interrupt on Change (RB7:RB4) ................ 4, 15, 28, 31RB0/INT Pin, External ............................... 4, 16, 28, 31TMR0 Overflow .................................................... <strong>18</strong>, 28Interrupts, Context Saving During ..................................... 29Interrupts, Enable <strong>Bit</strong>s<strong>Data</strong> <strong>EEPROM</strong> Write Complete Enable(EEIE <strong>Bit</strong>) ............................................................. 10, 29Global Interrupt Enable (GIE <strong>Bit</strong>) ............................... 10Interrupt on Change (RB7:RB4) Enable(RBIE <strong>Bit</strong>) ................................................................... 10RB0/INT Enable (INTE <strong>Bit</strong>) ........................................ 10TMR0 Overflow Enable (T0IE <strong>Bit</strong>) ............................. 10Interrupts, Flag <strong>Bit</strong>s ........................................................... 28<strong>Data</strong> <strong>EEPROM</strong> Write Complete Flag(EEIF <strong>Bit</strong>) ............................................................. 19, 29Interrupt on Change (RB7:RB4) Flag (RBIF <strong>Bit</strong>) ....... 10RB0/INT Flag (INTF <strong>Bit</strong>) ............................................ 10TMR0 Overflow Flag (T0IF <strong>Bit</strong>) .................................. 10KKeeLoq® Evaluation and Programming Tools .................. 38MMaster Clear (MCLR)MCLR Pin .....................................................................4MCLR Reset, Normal Operation ................................ 23MCLR Reset, SLEEP .......................................... 23, 31Memory Organization ...........................................................5<strong>Data</strong> <strong>EEPROM</strong> Memory ............................................ 19<strong>Data</strong> Memory ................................................................6Program Memory ..........................................................5Migration from Baseline to Midrange Devices ................... 62MPLAB Integrated Development EnvironmentSoftware ............................................................................ 37OOn-Line Support ................................................................ 65OPCODE Field Descriptions ............................................. 33OPTION_REG Register ................................. 7, 9, 16, <strong>18</strong>, 24INTEDG <strong>Bit</strong> ............................................................ 9, 29PS2:PS0 <strong>Bit</strong>s ......................................................... 9, 17PSA <strong>Bit</strong> .................................................................. 9, 17RBPU <strong>Bit</strong> ......................................................................9T0CS <strong>Bit</strong> .......................................................................9T0SE <strong>Bit</strong> .......................................................................9OSC1 Pin ..............................................................................4OSC2 Pin ..............................................................................4Oscillator Configuration ............................................... 21, 22HS ........................................................................ 22, 28LP ........................................................................ 22, 28RC ................................................................. 22, 23, 28Selection (FOSC1:FOSC0 <strong>Bit</strong>s) ................................ 21XT ........................................................................ 22, 28© 1998 Microchip Technology Inc. Preliminary DS35007A-page 63
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