PIC16F84A 18-pin Enhanced Flash/EEPROM 8-Bit MCU Data Sheet

More documents

Recommendations

Info

PIC16F84A6.7 Time-out Sequence and Power-downStatus Bits (TO/PD)On power-up (Figure 6-7, Figure 6-8, Figure 6-9 andFigure 6-10) the time-out sequence is as follows: FirstPWRT time-out is invoked after a POR has expired.Then the OST is activated. The total time-out will varybased on oscillator configuration and PWRTEconfiguration bit status. For example, in RC mode withthe PWRT disabled, there will be no time-out at all.TABLE 6-5OscillatorConfigurationTIME-OUT IN VARIOUSSITUATIONSSince the time-outs occur from the POR reset pulse, ifMCLR is kept low long enough, the time-outs willexpire. Then bringing MCLR high, execution will beginimmediately (Figure 6-7). This is useful for testingpurposes or to synchronize more than one PIC16F84Adevice when operating in parallel.Table 6-6 shows the significance of the TO and PD bits.Table 6-3 lists the reset conditions for some specialregisters, while Table 6-4 lists the reset conditions forall the registers.TABLE 6-6PWRTEnabledXT, HS, LP 72 ms +1024TOSCPower-upPWRTDisabled1024TOSCWake-upfromSLEEP1024TOSCRC 72 ms — —STATUS BITS AND THEIRSIGNIFICANCETO PD Condition1 1 Power-on Reset0 x Illegal, TO is set on PORx 0 Illegal, PD is set on POR0 1 WDT Reset (during normal operation)0 0 WDT Wake-up1 1 MCLR Reset during normal operation1 0 MCLR Reset during SLEEP or interruptwake-up from SLEEP6.8 InterruptsThe PIC16F84A has 4 sources of interrupt:• External interrupt RB0/INT pin• TMR0 overflow interrupt• PORTB change interrupts (pins RB7:RB4)• Data EEPROM write complete interruptThe interrupt control register (INTCON) recordsindividual interrupt requests in flag bits. It also containsthe individual and global interrupt enable bits.The global interrupt enable bit, GIE (INTCON)enables (if set) all un-masked interrupts or disables (ifcleared) all interrupts. Individual interrupts can bedisabled through their corresponding enable bits inINTCON register. Bit GIE is cleared on reset.The “return from interrupt” instruction, RETFIE, exitsinterrupt routine as well as sets the GIE bit, whichre-enable interrupts.The RB0/INT pin interrupt, the RB port change interruptand the TMR0 overflow interrupt flags are containedin the INTCON register.When an interrupt is responded to; the GIE bit iscleared to disable any further interrupt, the returnaddress is pushed onto the stack and the PC is loadedwith 0004h. For external interrupt events, such as theRB0/INT pin or PORTB change interrupt, the interruptlatency will be three to four instruction cycles. Theexact latency depends when the interrupt event occurs.The latency is the same for both one and two cycleinstructions. Once in the interrupt service routine thesource(s) of the interrupt can be determined by pollingthe interrupt flag bits. The interrupt flag bit(s) must becleared in software before re-enabling interrupts toavoid infinite interrupt requests.Note 1: Individual interrupt flag bits are setregardless of the status of theircorresponding mask bit or the GIE bit.FIGURE 6-11:T0IFT0IEINTFINTERBIFRBIEEEIFEEIEINTERRUPT LOGICWake-up(If in SLEEP mode)Interrupt to CPUGIEDS35007A-page 28 Preliminary © 1998 Microchip Technology Inc.
PIC16F84A6.8.1 INT INTERRUPTExternal interrupt on RB0/INT pin is edge triggered:either rising if INTEDG bit (OPTION_REG) is set,or falling, if INTEDG bit is clear. When a valid edgeappears on the RB0/INT pin, the INTF bit(INTCON) is set. This interrupt can be disabled byclearing control bit INTE (INTCON). Flag bit INTFmust be cleared in software via the interrupt serviceroutine before re-enabling this interrupt. The INTinterrupt can wake the processor from SLEEP(Section 6.11) only if the INTE bit was set prior to goinginto SLEEP. The status of the GIE bit decides whetherthe processor branches to the interrupt vectorfollowing wake-up.6.8.2 TMR0 INTERRUPTAn overflow (FFh → 00h) in TMR0 will set flag bit T0IF(INTCON). The interrupt can be enabled/disabledby setting/clearing enable bit T0IE (INTCON)(Section 4.0).6.8.3 PORB INTERRUPTAn input change on PORTB sets flag bit RBIF(INTCON). The interrupt can be enabled/disabledby setting/clearing enable bit RBIE (INTCON)(Section 3.2).Note 1: For a change on the I/O pin to berecognized, the pulse width must be atleast TCY wide.6.8.4 DATA EEPROM INTERRUPTAt the completion of a data EEPROM write cycle, flagbit EEIF (EECON1) will be set. The interrupt can beenabled/disabled by setting/clearing enable bit EEIE(INTCON) (Section 5.0).6.9 Context Saving During InterruptsDuring an interrupt, only the return PC value is savedon the stack. Typically, users wish to save key registervalues during an interrupt (e.g., W register and STATUSregister). This is implemented in software.Example 6-1 stores and restores the STATUS and Wregister’s values. The User defined registers, W_TEMPand STATUS_TEMP are the temporary storagelocations for the W and STATUS registers values.Example 6-1 does the following:a) Stores the W register.b) Stores the STATUS register in STATUS_TEMP.c) Executes the Interrupt Service Routine code.d) Restores the STATUS (and bank select bit)register.e) Restores the W register.EXAMPLE 6-1: SAVING STATUS AND W REGISTERS IN RAMPUSH MOVWF W_TEMP ; Copy W to TEMP register,SWAPF STATUS, W ; Swap status to be saved into WMOVWF STATUS_TEMP ; Save status to STATUS_TEMP registerISR : :: ; Interrupt Service Routine: ; should configure Bank as required: ;POP SWAPF STATUS_TEMP, W ; Swap nibbles in STATUS_TEMP register; and place result into WMOVWF STATUS ; Move W into STATUS register; (sets bank to original state)SWAPF W_TEMP, F ; Swap nibbles in W_TEMP and place result in W_TEMPSWAPF W_TEMP, W ; Swap nibbles in W_TEMP and place result into W© 1998 Microchip Technology Inc. Preliminary DS35007A-page 29
Page 1 and 2: MPIC16F84A18-pin Enhanced Flash/EEP
Page 3 and 4: PIC16F84A1.0 DEVICE OVERVIEWThis do
Page 5 and 6: PIC16F84A2.0 MEMORY ORGANIZATIONThe
Page 7 and 8: PIC16F84A2.2.2 SPECIAL FUNCTION REG
Page 9 and 10: PIC16F84A2.2.2.2 OPTION_REG REGISTE
Page 11 and 12: PIC16F84A2.3 PCL and PCLATHThe prog
Page 13 and 14: PIC16F84A3.0 I/O PORTSSome pins for
Page 15 and 16: PIC16F84A3.2 PORTB and TRISB Regist
Page 17 and 18: PIC16F84A4.0 TIMER0 MODULEThe Timer
Page 19 and 20: PIC16F84A5.0 DATA EEPROM MEMORYThe
Page 21 and 22: PIC16F84A6.0 SPECIAL FEATURES OF TH
Page 23 and 24: PIC16F84A6.2.3 RC OSCILLATORFor tim
Page 25 and 26: PIC16F84A6.4 Power-on Reset (POR)A
Page 27: PIC16F84AFIGURE 6-9:TIME-OUT SEQUEN
Page 31 and 32: PIC16F84A6.11 Power-down Mode (SLEE
Page 33 and 34: PIC16F84A7.0 INSTRUCTION SET SUMMAR
Page 35 and 36: PIC16F84A8.0 DEVELOPMENT SUPPORT8.1
Page 37 and 38: PIC16F84A8.10 MPLAB Integrated Deve
Page 39 and 40: © 1998 Microchip Technology Inc. P
Page 41 and 42: PIC16F84A9.0 ELECTRICAL CHARACTERIS
Page 43 and 44: PIC16F84A9.1 DC CHARACTERISTICS: PI
Page 45 and 46: PIC16F84A9.3 DC CHARACTERISTICS: PI
Page 47 and 48: PIC16F84A9.5 AC (Timing) Characteri
Page 49 and 50: PIC16F84A9.5.3 TIMING DIAGRAMS AND
Page 51 and 52: PIC16F84AFIGURE 9-5:RESET, WATCHDOG
Page 53 and 54: PIC16F84A10.0 DC & AC CHARACTERISTI
Page 55 and 56: PIC16F84A11.0 PACKAGING INFORMATION
Page 57 and 58: PIC16F84A11.3 K04-051 18-Lead Plast
Page 59 and 60: PIC16F84AAPPENDIX A: REVISION HISTO
Page 61 and 62: PIC16F84ANOTES:© 1998 Microchip Te
Page 63 and 64: PIC16F84AINDEXAAbsolute Maximum Rat
Page 65 and 66: PIC16F84AON-LINE SUPPORTMicrochip p
Page 67 and 68: PIC16F84APIC16F84A PRODUCT IDENTIFI

PIC16F84A 18-pin Enhanced Flash/EEPROM 8-Bit MCU Data Sheet

Create successful ePaper yourself

Delete template?

Save as template?