PIC16F84A 18-pin Enhanced Flash/EEPROM 8-Bit MCU Data Sheet

PIC16F84ATABLE 7-2Mnemonic,OperandsPIC16CXXX INSTRUCTION SETDescription Cycles 14-Bit Opcode StatusMSbLSbAffectedNotesADDWFANDWFCLRFCLRWCOMFDECFDECFSZINCFINCFSZIORWFMOVFMOVWFNOPRLFRRFSUBWFSWAPFXORWFBCFBSFBTFSCBTFSSADDLWANDLWCALLCLRWDTGOTOIORLWMOVLWRETFIERETLWRETURNSLEEPSUBLWXORLWf, df, df-f, df, df, df, df, df, df, df-f, df, df, df, df, df, bf, bf, bf, bkkk-kkk-k--kkAdd W and fAND W with fClear fClear WComplement fDecrement fDecrement f, Skip if 0Increment fIncrement f, Skip if 0Inclusive OR W with fMove fMove W to fNo OperationRotate Left f through CarryRotate Right f through CarrySubtract W from fSwap nibbles in fExclusive OR W with fBit Clear fBit Set fBit Test f, Skip if ClearBit Test f, Skip if SetAdd literal and WAND literal with WCall subroutineClear Watchdog TimerGo to addressInclusive OR literal with WMove literal to WReturn from interruptReturn with literal in WReturn from SubroutineGo into standby modeSubtract W from literalExclusive OR literal with WBYTE-ORIENTED FILE REGISTER OPERATIONS1111111(2)11(2)111111111000000000000000000000000000000000000BIT-ORIENTED FILE REGISTER OPERATIONS111 (2)1 (2)01010101LITERAL AND CONTROL OPERATIONS11212112221111111100010111100110000111101110101000100011001001110111010111101001000000000001101110000101110011000bb01bb10bb11bb111x10010kkk00001kkk100000xx000001xx00000000110x1010dfffdffflfff0xxxdfffdfffdfffdfffdfffdfffdffflfff0xx0dfffdfffdfffdfffdfffbfffbfffbfffbfffkkkkkkkkkkkk0110kkkkkkkkkkkk0000kkkk00000110kkkkkkkkffffffffffffxxxxffffffffffffffffffffffffffffffff0000ffffffffffffffffffffffffffffffffffffkkkkkkkkkkkk0100kkkkkkkkkkkk1001kkkk10000011kkkkkkkkC,DC,ZZZZZZZZZCCC,DC,ZZC,DC,ZZTO,PDZTO,PDC,DC,ZZNote 1: When an I/O register is modified as a function of itself ( e.g., MOVF PORTB, 1), the value used will be that value presenton the pins themselves. For example, if the data latch is '1' for a pin configured as input and is driven low by an externaldevice, the data will be written back with a '0'.2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assignedto the Timer0 Module.3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle isexecuted as a NOP.1,21,221,21,21,2,31,21,2,31,21,21,21,21,21,21,21,21,233DS35007A-page 34 Preliminary © 1998 Microchip Technology Inc.