NASA Scientific and Technical Aerospace Reports

In this paper, we develop a time and its corresponding spatial discretization scheme, based upon the assumption of a
certain weak singularity of parallel ut(t) parallel Lz(omega) = parallel ut parallel2, for the discontinuous Galerkin finite
element method for one-dimensional parabolic problems. Optimal convergence rates in both time and spatial variables are
obtained. A discussion of automatic time-step control method is also included.
Author
Finite Element Method; Galerkin Method; Discontinuity; Parabolic Differential Equations; Mathematical Models; Problem
Solving
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COMPUTER OPERATIONS AND HARDWARE
Includes hardware for computer graphics, firmware and data processing. For components see 33 Electronics and Electrical Engineering.
For computer vision see 63 Cybernetics, Artificial Intelligence and Robotics.
20040068174 North Carolina Agricultural and Technical State Univ., Greensboro, NC, USA
An Approach for Self-Timed Synchronous CMOS Circuit Design
Walker, Alvernon; Lala, Parag K.; May 17, 2001; 5 pp.; In English
Contract(s)/Grant(s): NAG5-7158; No Copyright; Avail: CASI; A01, Hardcopy
In this letter we present a timing and control strategy that can be used to realize synchronous systems with a level of
performance that approaches that of asynchronous circuits or systems. This approach is based upon a single-phase
synchronous circuit/system architecture with a variable period clock. The handshaking signals required for asynchronous
self-timed circuits are not needed. Dynamic power supply current monitoring is used to generate the timing information, that
is comparable to the completion signal found in self-timed circuits; this timing information is used to modi@ the circuit clock
period. This letter is concluded with an example of the proposed approach applied to a static CMOS ripple-carry adder.
Author
Architecture (Computers); Circuits; Clocks; Time Synchronization; Time
20040068175 North Carolina Agricultural and Technical State Univ., Greensboro, NC, USA
A Step Response Based Mixed-Signal BIST Approach for Continuous-time Linear Circuits
Walker, Alvernon; Lala, P. K.; May 17, 2001; 7 pp.; In English
Contract(s)/Grant(s): NAG5-7158; No Copyright; Avail: CASI; A02, Hardcopy
A new Mixed-Signal Built-in self-test approach that is based upon the step response of a reconfigurable (or multifunction)
analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT)
for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two
CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require
an analog-to-digital converter (ADC) and/or digital-to-analog converter(DAC). It also does not require any precision voltage
sources or comparators. This approach does not require any additional analog circuits to realize the test signal generator and
sample circuits. The paper is concluded with the application of the proposed approach to a circuit found in the work of Epstein
et al and two ITC 97 analog benchmark circuits.
Author
Analog Circuits; Electronic Equipment Tests; Fault Detection; Reliability Engineering; Self Tests
20040068176 North Carolina Agricultural and Technical State Univ., Greensboro, NC, USA
A Step Response Based Mixed-Signal BIST Approach
Walker, Alvernon; May 17, 2001; 10 pp.; In English
Contract(s)/Grant(s): NAG5-7158; No Copyright; Avail: CASI; A02, Hardcopy
A new Mixed-Signal Built-in Self-test approach that is based upon the step response of a reconfigurable (or multifunction)
analog block is presented in this paper. The technique requires the overlapping step response of the Circuit Under Test (CUT)
for two circuit configurations. Each configuration can be realized by changing the topology of the CUT or by sampling two
CUT nodes with differing step responses. The technique can effectively detect both soft and hard faults and does not require
an analog-to-digital converter (ADC) and/or digital-to-analog converter( DAC). It also does not require any precision voltage
sources or comparators. The approach does not require any additional analog circuits to realize the test signal generator and
a two input analog multiplexer for CUT test node sampling. The paper is concluded with the application of the proposed
187