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View File - University of Engineering and Technology, Taxila

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TABLE 3.28-PSK Truth TableInput bitsTransmitted phase symbols111 22.5 110 67.5 101 157.5 100 112.5 011 337.5 010 292.5 001 247.5 000 202.5 carrier in (3.1) can take on one <strong>of</strong> eight values: 22.5 , 67.5 , 112.5 , 157.5 ,202.5 , 247.5 , 292.5 , or 337.5 , each representing three-input bits as shownin Table 3.2. A schematic diagram <strong>of</strong> an 8-PSK modulator is shown in Fig.3.6.The incoming serial bit stream enters the bit splitter (demultiplexer),where it is converted to a parallel, three-channel output: I-(in-phase) channel,Q-(in-quadrature) channel, <strong>and</strong> the control x-channel. Consequently, the bitrate in each <strong>of</strong> the channels is r b =3, since b ¼ 3. The bits in the I- <strong>and</strong> Q-channels enter the level (digital-to-analog) converters.The converted output data are fed to the balanced product modulatorswith input carriers’ relative phase <strong>of</strong> 0 <strong>and</strong> 90 to the I- <strong>and</strong> Q-channels,respectively. The outputs <strong>of</strong> the product modulators are fed to the bitcombiningcircuit (linear summer), where they are converted from the I-FIGURE 3.6An 8-PSK modulator.Copyright © 2002 by Marcel Dekker, Inc. All Rights Reserved.

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