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View File - University of Engineering and Technology, Taxila

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FIGURE 6.6 Trellis diagram <strong>of</strong> Fig. 6.4. The solid line denotes the output generatedby the input bit ‘‘0’’ whereas the dotted line denotes the output generated by the inputbit ‘‘1’’. Labels a, b, c, <strong>and</strong> d denote the four possible states <strong>of</strong> the shift register.FIGURE 6.7 The state diagram <strong>of</strong> Fig. 6.4. The solid lines denote that the input bit is‘‘0’’ whereas the dotted lines denote that the input bit is ‘‘1’’. The three bits appended toeach transitory line represent the output bits.Copyright © 2002 by Marcel Dekker, Inc. All Rights Reserved.

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