View File - University of Engineering and Technology, Taxila

FIGURE 6.3Rate 1/2 convolutional encoder.samples the two mod-2 adder outputs. This process continues until eventuallythe last bit of the message (input) bits has been entered into r 0 . Thereafter, toensure that every input data bit may proceed entirely through the shift register,and hence be involved in the complete coding process, enough zeros ‘‘0’’ areadded to the message to transfer the last message bit through r 2 and, thus, outof the shift register. The shift register finds itself in its initial all-zero state (asin Table 6.2, Column 1, Shift 8). This may be verified, by an example.If the input stream to the encoder is a five-bit sequence:x ¼ 10111ð6:33aÞthen the coded output bit stream is (see Table 6.2)ab ¼ 11 11 10 00 01 10 01 00ð6:33bÞTABLE 6.2Table of Register Contents for DecodingShift Input bit r 0 r 1 r 2 ab1 1 100 112 0 010 113 1 101 104 1 110 005 1 111 016 0 011 107 0 001 018 0 000 00 resetCopyright © 2002 by Marcel Dekker, Inc. All Rights Reserved.