View File - University of Engineering and Technology, Taxila

FIGURE 3.12 Principle of scrambling and descrambling: (a) scrambler; (b)descrambler.error into the feedforward connection affects a successive number of bits equalto the shift-register length, while for the feedback connection the effect can bemuch longer.Each scrambler and descrambler (in Fig. 3.12, for example) employs afour-stage shift register (b i 1 ; b i 2 ; b i 3 , and b i 4 ) with appropriate butembedded tap gains and omitting a clock line. The clock clicks whenever abit sequence enters the register and shifts from one stage to the next. Thebinary message sequence s i at the input to the scrambler is mod-2 added to theoutput of the register y i to form the scrambled message, which is also fed backto the register input b i 1 . Thus, the scrambling operation can be written asy i ¼ b i 3 b i 4s i ¼ s i y ið3:24ÞThe descrambler is a feedforward connected shift register. It essentiallyreverses the structure of the scrambler and reproduces the original inputmessage sequence becauses i y i ¼ðs i y i Þy i¼ s i ðy i y i Þ¼ s i 0 ¼ s ið3:25ÞEquations (3.24) and (3.25) hold for any shift-register arrangement as long asthe scrambler and descrambler have identical registers.Copyright © 2002 by Marcel Dekker, Inc. All Rights Reserved.