UltraScale Architecture Memory Resources

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Chapter 1: Block RAM Resources There is no dedicated monitor to arbitrate the effect of identical addresses on both ports. IMPORTANT: The two clocks must be timed appropriately. Conflicting simultaneous writes to the same location never cause any physical damage but can result in data uncertainty. X-Ref Target - Figure 1-1 CASDOUTPA CASDOUTA Sleep 32 4 15 4 32 4 15 4 CASDINA CASDINPA 32 4 32 4 36-Kbit Block RAM DINA DINPA ADDRA Port A WEA ENA ADDRENA RSTREGA RSTRAMA DOUTA CLKA DOUTPA REGCEA 36 Kb Memory Array DINB DINPB ADDRB WEB ENB Port B ADDRENB RSTREGB RSTRAMB CLKB REGCEB DOUTB DOUTPB 32 4 32 4 CASDOUTB CASDOUTPB 32 4 32 4 CASDINPB CASDINB UG573_c1_01_060613 Figure 1-1: RAMB36 Usage in a True Dual-Port Data Flow Table 1-2: Port Function DIN[A|B] DINP[A|B] (1) ADDR[A|B] ADDREN[A|B] WE[A|B] EN[A|B] RSTREG[A|B] True Dual-Port Functions and Descriptions Data input bus. Description Data input parity bus. Can be used for additional data inputs. Address bus. Address latching enable. If Low, the old address is latched. Byte-wide write enable. When inactive, no data is written to the block RAM and the output bus remains in its previous state. Synchronous set/reset of the output registers (DO_REG = 1). The RSTREG_PRIORITY attribute determines the priority over REGCE. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 10 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources Table 1-2: True Dual-Port Functions and Descriptions (Cont’d) Port Function Description RSTRAM[A|B] CLK[A|B] DOUT[A|B] DOUTP[A|B] (1) REGCE[A|B] CASDIN[A|B] CASDINP[A|B] CASDOUT[A|B] CASDOUTP[A|B] SLEEP Read Operation In latch mode, the read operation uses one clock edge. The read address is registered on the read port, and the stored data is loaded into the output latches after the RAM access time. When using the output register, the read operation takes one extra latency cycle. Write Operation A write operation is a single clock-edge operation. The write address is registered on the write port, and the data input is stored in memory. Write Modes Synchronous set/reset of the output data latches. Clock input. Data output bus. Data output parity bus. Can be used for additional data outputs. Output register clock enable. Cascade data input bus. Cascade parity input bus. Cascade data output bus. Cascade parity output bus. Dynamic shutdown power saving. If SLEEP is active, the block is in power saving mode. Notes: 1. Data-In Buses – DINADIN, DINPADINP, DINBDIN, and DINPBDINP, page 31 has more information on data parity pins. 2. Block RAM primitive port names can be different from the port function names. 3. For a more complete cascade data flow and port descriptions, see Cascadable Block RAM, page 16 and Block RAM Library Primitives, page 24. Three settings of the write mode determine the behavior of the data available on the output latches after a write clock edge: WRITE_FIRST, READ_FIRST, and NO_CHANGE. Write mode selection is set by configuration. The write mode attribute can be individually selected for each port. The default mode is WRITE_FIRST. WRITE_FIRST outputs the newly written data onto the output bus. READ_FIRST outputs the previously stored data while new data is being written. NO_CHANGE maintains the output previously generated by a read operation. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 11 UG573 (v1.2) February 24, 2015
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Page 41 and 42: Chapter 1: Block RAM Resources Read
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Chapter 2: Built-in FIFO Table 2-6:
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Chapter 2: Built-in FIFO FIFO18/36
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Chapter 2: Built-in FIFO • MIDDLE
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Chapter 2: Built-in FIFO FWFT Mode
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Chapter 2: Built-in FIFO FIFO might
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Chapter 2: Built-in FIFO the status
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Chapter 2: Built-in FIFO X-Ref Targ
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Chapter 2: Built-in FIFO Figure 2-1
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Chapter 3: Built-in Error Correctio
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Appendix A Additional Resources and
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