UltraScale Architecture Memory Resources

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Chapter 1: Block RAM Resources Address Enable This feature allows the new address to be captured only when address EN is High. If the address EN is Low, the old address remains internally latched and is used for internal access. Any change in address input is ignored. This feature is controlled by the ENADDREN attribute. See Figure 1-12. X-Ref Target - Figure 1-12Figure 1-12Figure 1-12 ADDR[0] 0 1 ADDR[0] Register ADDR[0] ADDR[n] 0 1 ADDR[n] Register ADDR[N] ADDREN CLK UG573_c1_12_020713 Figure 1-12: Address Latching Enable UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 22 UG573 (v1.2) February 24, 2015
Chapter 1: Block RAM Resources Byte-Wide Write Enable The byte-wide write enable feature of the block RAM enables the writing of eight-bit (one byte) portions of incoming data. There are four independent byte-wide write enable inputs to the RAMB36E2 true dual-port RAM. In TDP mode for RAMB36E2, there are two ports, A and B, each of which have a 4-bit write enable bus (one bit corresponding to each data byte). In SDP mode for RAMB36E2, there is one write port, which has an 8-bit write enable bus (one bit corresponding to each data byte). Table 1-4 summarizes the byte-wide write enables for the 36 Kb and 18 Kb block RAM. Each byte-wide write enable is associated with one byte of input data and one parity bit. The byte-wide write enable inputs must be driven in accordance with the data width configurations. This feature is useful when using block RAM to interface with a microprocessor. Byte-wide write enable is not available in the ECC mode. Byte-wide write enable is further described in Additional RAMB18E2 and RAMB36E2 Primitive Design Considerations, page 45. Figure 1-13 shows the byte-wide write enable timing diagram for the RAMB36E2. X-Ref Target - Figure 1-13 CLK WE DIN 1111 0011 XXXX 1111 2222 XXXX ADDR aa bb bb cc DOUT 0000 MEM(aa) 1111 1122 MEM(cc) EN Disabled Read Write MEM(bb)=1111 Byte Write MEM(bb)=1122 Read UG573_c1_13_060613 Figure 1-13: Byte-wide Write Operation Waveforms (x36 WRITE_FIRST) Table 1-4: Available Byte-Wide Write Enables Primitive Maximum Bit Width Number of Byte-Wide Write Enables RAMB36E2 TDP usage 36 4 RAMB36E2 SDP usage 72 8 RAMB18E2 TDP usage 18 2 RAMB18E2 SDP usage 36 4 When the RAMB36E2 is configured for a 36-bit or 18-bit wide datapath, any port can restrict writing to specified byte locations within the data word. If configured in READ_FIRST mode, the DOUT bus shows the previous content of the whole addressed word. In WRITE_FIRST mode, DOUT shows a combination of the newly written enabled byte(s), and the initial memory contents of the unwritten bytes. UltraScale Architecture Memory Resources www.xilinx.com Send Feedback 23 UG573 (v1.2) February 24, 2015
Page 1 and 2: UltraScale Architecture Memory Reso
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Chapter 2: Built-in FIFO the status
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Chapter 2: Built-in FIFO X-Ref Targ
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Chapter 2: Built-in FIFO Figure 2-1
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Appendix A Additional Resources and
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